// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018 Rockchip Electronics Co. Ltd. * * Author: Wyon Bi <[email protected]> */ #include <linux/bits.h> #include <linux/kernel.h> #include <linux/clk.h> #include <linux/iopoll.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <linux/time64.h> #include <linux/phy/phy.h> #include <linux/phy/phy-mipi-dphy.h> #define UPDATE(x, h, l) … /* * The offset address[7:0] is distributed two parts, one from the bit7 to bit5 * is the first address, the other from the bit4 to bit0 is the second address. * when you configure the registers, you must set both of them. The Clock Lane * and Data Lane use the same registers with the same second address, but the * first address is different. */ #define FIRST_ADDRESS(x) … #define SECOND_ADDRESS(x) … #define PHY_REG(first, second) … /* Analog Register Part: reg00 */ #define BANDGAP_POWER_MASK … #define BANDGAP_POWER_DOWN … #define BANDGAP_POWER_ON … #define LANE_EN_MASK … #define LANE_EN_CK … #define LANE_EN_3 … #define LANE_EN_2 … #define LANE_EN_1 … #define LANE_EN_0 … #define POWER_WORK_MASK … #define POWER_WORK_ENABLE … #define POWER_WORK_DISABLE … /* Analog Register Part: reg01 */ #define REG_SYNCRST_MASK … #define REG_SYNCRST_RESET … #define REG_SYNCRST_NORMAL … #define REG_LDOPD_MASK … #define REG_LDOPD_POWER_DOWN … #define REG_LDOPD_POWER_ON … #define REG_PLLPD_MASK … #define REG_PLLPD_POWER_DOWN … #define REG_PLLPD_POWER_ON … /* Analog Register Part: reg03 */ #define REG_FBDIV_HI_MASK … #define REG_FBDIV_HI(x) … #define REG_PREDIV_MASK … #define REG_PREDIV(x) … /* Analog Register Part: reg04 */ #define REG_FBDIV_LO_MASK … #define REG_FBDIV_LO(x) … /* Analog Register Part: reg05 */ #define SAMPLE_CLOCK_PHASE_MASK … #define SAMPLE_CLOCK_PHASE(x) … #define CLOCK_LANE_SKEW_PHASE_MASK … #define CLOCK_LANE_SKEW_PHASE(x) … /* Analog Register Part: reg06 */ #define DATA_LANE_3_SKEW_PHASE_MASK … #define DATA_LANE_3_SKEW_PHASE(x) … #define DATA_LANE_2_SKEW_PHASE_MASK … #define DATA_LANE_2_SKEW_PHASE(x) … /* Analog Register Part: reg07 */ #define DATA_LANE_1_SKEW_PHASE_MASK … #define DATA_LANE_1_SKEW_PHASE(x) … #define DATA_LANE_0_SKEW_PHASE_MASK … #define DATA_LANE_0_SKEW_PHASE(x) … /* Analog Register Part: reg08 */ #define PLL_POST_DIV_ENABLE_MASK … #define PLL_POST_DIV_ENABLE … #define SAMPLE_CLOCK_DIRECTION_MASK … #define SAMPLE_CLOCK_DIRECTION_REVERSE … #define SAMPLE_CLOCK_DIRECTION_FORWARD … #define LOWFRE_EN_MASK … #define PLL_OUTPUT_FREQUENCY_DIV_BY_1 … #define PLL_OUTPUT_FREQUENCY_DIV_BY_2 … /* Analog Register Part: reg0b */ #define CLOCK_LANE_VOD_RANGE_SET_MASK … #define CLOCK_LANE_VOD_RANGE_SET(x) … #define VOD_MIN_RANGE … #define VOD_MID_RANGE … #define VOD_BIG_RANGE … #define VOD_MAX_RANGE … /* Analog Register Part: reg1E */ #define PLL_MODE_SEL_MASK … #define PLL_MODE_SEL_LVDS_MODE … #define PLL_MODE_SEL_MIPI_MODE … /* Digital Register Part: reg00 */ #define REG_DIG_RSTN_MASK … #define REG_DIG_RSTN_NORMAL … #define REG_DIG_RSTN_RESET … /* Digital Register Part: reg01 */ #define INVERT_TXCLKESC_MASK … #define INVERT_TXCLKESC_ENABLE … #define INVERT_TXCLKESC_DISABLE … #define INVERT_TXBYTECLKHS_MASK … #define INVERT_TXBYTECLKHS_ENABLE … #define INVERT_TXBYTECLKHS_DISABLE … /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */ #define T_LPX_CNT_MASK … #define T_LPX_CNT(x) … /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */ #define T_HS_ZERO_CNT_HI_MASK … #define T_HS_ZERO_CNT_HI(x) … #define T_HS_PREPARE_CNT_MASK … #define T_HS_PREPARE_CNT(x) … /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */ #define T_HS_ZERO_CNT_LO_MASK … #define T_HS_ZERO_CNT_LO(x) … /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */ #define T_HS_TRAIL_CNT_MASK … #define T_HS_TRAIL_CNT(x) … /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */ #define T_HS_EXIT_CNT_LO_MASK … #define T_HS_EXIT_CNT_LO(x) … /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */ #define T_CLK_POST_CNT_LO_MASK … #define T_CLK_POST_CNT_LO(x) … /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */ #define LPDT_TX_PPI_SYNC_MASK … #define LPDT_TX_PPI_SYNC_ENABLE … #define LPDT_TX_PPI_SYNC_DISABLE … #define T_WAKEUP_CNT_HI_MASK … #define T_WAKEUP_CNT_HI(x) … /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */ #define T_WAKEUP_CNT_LO_MASK … #define T_WAKEUP_CNT_LO(x) … /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */ #define T_CLK_PRE_CNT_MASK … #define T_CLK_PRE_CNT(x) … /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */ #define T_CLK_POST_CNT_HI_MASK … #define T_CLK_POST_CNT_HI(x) … #define T_TA_GO_CNT_MASK … #define T_TA_GO_CNT(x) … /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */ #define T_HS_EXIT_CNT_HI_MASK … #define T_HS_EXIT_CNT_HI(x) … #define T_TA_SURE_CNT_MASK … #define T_TA_SURE_CNT(x) … /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */ #define T_TA_WAIT_CNT_MASK … #define T_TA_WAIT_CNT(x) … /* LVDS Register Part: reg00 */ #define LVDS_DIGITAL_INTERNAL_RESET_MASK … #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE … #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE … /* LVDS Register Part: reg01 */ #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK … #define LVDS_DIGITAL_INTERNAL_ENABLE … #define LVDS_DIGITAL_INTERNAL_DISABLE … /* LVDS Register Part: reg03 */ #define MODE_ENABLE_MASK … #define TTL_MODE_ENABLE … #define LVDS_MODE_ENABLE … #define MIPI_MODE_ENABLE … /* LVDS Register Part: reg0b */ #define LVDS_LANE_EN_MASK … #define LVDS_DATA_LANE0_EN … #define LVDS_DATA_LANE1_EN … #define LVDS_DATA_LANE2_EN … #define LVDS_DATA_LANE3_EN … #define LVDS_CLK_LANE_EN … #define LVDS_PLL_POWER_MASK … #define LVDS_PLL_POWER_OFF … #define LVDS_PLL_POWER_ON … #define LVDS_BANDGAP_POWER_MASK … #define LVDS_BANDGAP_POWER_DOWN … #define LVDS_BANDGAP_POWER_ON … #define DSI_PHY_RSTZ … #define PHY_ENABLECLK … #define DSI_PHY_STATUS … #define PHY_LOCK … enum phy_max_rate { … }; struct inno_video_phy_plat_data { … }; struct inno_dsidphy { … }; enum { … }; struct inno_mipi_dphy_timing { … }; static const struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = …; static const struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = …; static void phy_update_bits(struct inno_dsidphy *inno, u8 first, u8 second, u8 mask, u8 val) { … } static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno, unsigned long rate) { … } static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) { … } static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) { … } static int inno_dsidphy_power_on(struct phy *phy) { … } static int inno_dsidphy_power_off(struct phy *phy) { … } static int inno_dsidphy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { … } static int inno_dsidphy_configure(struct phy *phy, union phy_configure_opts *opts) { … } static const struct phy_ops inno_dsidphy_ops = …; static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = …; static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = …; static int inno_dsidphy_probe(struct platform_device *pdev) { … } static void inno_dsidphy_remove(struct platform_device *pdev) { … } static const struct of_device_id inno_dsidphy_of_match[] = …; MODULE_DEVICE_TABLE(of, inno_dsidphy_of_match); static struct platform_driver inno_dsidphy_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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