/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers. * * Copyright (C) 2016 David Lechner <[email protected]> */ #ifndef __LINUX_MFD_DA8XX_CFGCHIP_H #define __LINUX_MFD_DA8XX_CFGCHIP_H #include <linux/bitops.h> /* register offset (32-bit registers) */ #define CFGCHIP(n) … /* CFGCHIP0 (PLL0/EDMA3_0) register bits */ #define CFGCHIP0_PLL_MASTER_LOCK … #define CFGCHIP0_EDMA30TC1DBS(n) … #define CFGCHIP0_EDMA30TC1DBS_MASK … #define CFGCHIP0_EDMA30TC1DBS_16 … #define CFGCHIP0_EDMA30TC1DBS_32 … #define CFGCHIP0_EDMA30TC1DBS_64 … #define CFGCHIP0_EDMA30TC0DBS(n) … #define CFGCHIP0_EDMA30TC0DBS_MASK … #define CFGCHIP0_EDMA30TC0DBS_16 … #define CFGCHIP0_EDMA30TC0DBS_32 … #define CFGCHIP0_EDMA30TC0DBS_64 … /* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */ #define CFGCHIP1_CAP2SRC(n) … #define CFGCHIP1_CAP2SRC_MASK … #define CFGCHIP1_CAP2SRC_ECAP_PIN … #define CFGCHIP1_CAP2SRC_MCASP0_TX … #define CFGCHIP1_CAP2SRC_MCASP0_RX … #define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD … #define CFGCHIP1_CAP2SRC_EMAC_C0_RX … #define CFGCHIP1_CAP2SRC_EMAC_C0_TX … #define CFGCHIP1_CAP2SRC_EMAC_C0_MISC … #define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD … #define CFGCHIP1_CAP2SRC_EMAC_C1_RX … #define CFGCHIP1_CAP2SRC_EMAC_C1_TX … #define CFGCHIP1_CAP2SRC_EMAC_C1_MISC … #define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD … #define CFGCHIP1_CAP2SRC_EMAC_C2_RX … #define CFGCHIP1_CAP2SRC_EMAC_C2_TX … #define CFGCHIP1_CAP2SRC_EMAC_C2_MISC … #define CFGCHIP1_CAP1SRC(n) … #define CFGCHIP1_CAP1SRC_MASK … #define CFGCHIP1_CAP1SRC_ECAP_PIN … #define CFGCHIP1_CAP1SRC_MCASP0_TX … #define CFGCHIP1_CAP1SRC_MCASP0_RX … #define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD … #define CFGCHIP1_CAP1SRC_EMAC_C0_RX … #define CFGCHIP1_CAP1SRC_EMAC_C0_TX … #define CFGCHIP1_CAP1SRC_EMAC_C0_MISC … #define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD … #define CFGCHIP1_CAP1SRC_EMAC_C1_RX … #define CFGCHIP1_CAP1SRC_EMAC_C1_TX … #define CFGCHIP1_CAP1SRC_EMAC_C1_MISC … #define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD … #define CFGCHIP1_CAP1SRC_EMAC_C2_RX … #define CFGCHIP1_CAP1SRC_EMAC_C2_TX … #define CFGCHIP1_CAP1SRC_EMAC_C2_MISC … #define CFGCHIP1_CAP0SRC(n) … #define CFGCHIP1_CAP0SRC_MASK … #define CFGCHIP1_CAP0SRC_ECAP_PIN … #define CFGCHIP1_CAP0SRC_MCASP0_TX … #define CFGCHIP1_CAP0SRC_MCASP0_RX … #define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD … #define CFGCHIP1_CAP0SRC_EMAC_C0_RX … #define CFGCHIP1_CAP0SRC_EMAC_C0_TX … #define CFGCHIP1_CAP0SRC_EMAC_C0_MISC … #define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD … #define CFGCHIP1_CAP0SRC_EMAC_C1_RX … #define CFGCHIP1_CAP0SRC_EMAC_C1_TX … #define CFGCHIP1_CAP0SRC_EMAC_C1_MISC … #define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD … #define CFGCHIP1_CAP0SRC_EMAC_C2_RX … #define CFGCHIP1_CAP0SRC_EMAC_C2_TX … #define CFGCHIP1_CAP0SRC_EMAC_C2_MISC … #define CFGCHIP1_HPIBYTEAD … #define CFGCHIP1_HPIENA … #define CFGCHIP0_EDMA31TC0DBS(n) … #define CFGCHIP0_EDMA31TC0DBS_MASK … #define CFGCHIP0_EDMA31TC0DBS_16 … #define CFGCHIP0_EDMA31TC0DBS_32 … #define CFGCHIP0_EDMA31TC0DBS_64 … #define CFGCHIP1_TBCLKSYNC … #define CFGCHIP1_AMUTESEL0(n) … #define CFGCHIP1_AMUTESEL0_MASK … #define CFGCHIP1_AMUTESEL0_LOW … #define CFGCHIP1_AMUTESEL0_BANK_0 … #define CFGCHIP1_AMUTESEL0_BANK_1 … #define CFGCHIP1_AMUTESEL0_BANK_2 … #define CFGCHIP1_AMUTESEL0_BANK_3 … #define CFGCHIP1_AMUTESEL0_BANK_4 … #define CFGCHIP1_AMUTESEL0_BANK_5 … #define CFGCHIP1_AMUTESEL0_BANK_6 … #define CFGCHIP1_AMUTESEL0_BANK_7 … /* CFGCHIP2 (USB PHY) register bits */ #define CFGCHIP2_PHYCLKGD … #define CFGCHIP2_VBUSSENSE … #define CFGCHIP2_RESET … #define CFGCHIP2_OTGMODE(n) … #define CFGCHIP2_OTGMODE_MASK … #define CFGCHIP2_OTGMODE_NO_OVERRIDE … #define CFGCHIP2_OTGMODE_FORCE_HOST … #define CFGCHIP2_OTGMODE_FORCE_DEVICE … #define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW … #define CFGCHIP2_USB1PHYCLKMUX … #define CFGCHIP2_USB2PHYCLKMUX … #define CFGCHIP2_PHYPWRDN … #define CFGCHIP2_OTGPWRDN … #define CFGCHIP2_DATPOL … #define CFGCHIP2_USB1SUSPENDM … #define CFGCHIP2_PHY_PLLON … #define CFGCHIP2_SESENDEN … #define CFGCHIP2_VBDTCTEN … #define CFGCHIP2_REFFREQ(n) … #define CFGCHIP2_REFFREQ_MASK … #define CFGCHIP2_REFFREQ_12MHZ … #define CFGCHIP2_REFFREQ_24MHZ … #define CFGCHIP2_REFFREQ_48MHZ … #define CFGCHIP2_REFFREQ_19_2MHZ … #define CFGCHIP2_REFFREQ_38_4MHZ … #define CFGCHIP2_REFFREQ_13MHZ … #define CFGCHIP2_REFFREQ_26MHZ … #define CFGCHIP2_REFFREQ_20MHZ … #define CFGCHIP2_REFFREQ_40MHZ … /* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */ #define CFGCHIP3_RMII_SEL … #define CFGCHIP3_UPP_TX_CLKSRC … #define CFGCHIP3_PLL1_MASTER_LOCK … #define CFGCHIP3_ASYNC3_CLKSRC … #define CFGCHIP3_PRUEVTSEL … #define CFGCHIP3_DIV45PENA … #define CFGCHIP3_EMA_CLKSRC … /* CFGCHIP4 (McASP0 AMUNTEIN) register bits */ #define CFGCHIP4_AMUTECLR0 … #endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */
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