/* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "dm_services.h" #include "dc.h" #include "dcn31/dcn31_init.h" #include "resource.h" #include "include/irq_service_interface.h" #include "dcn315_resource.h" #include "dcn20/dcn20_resource.h" #include "dcn30/dcn30_resource.h" #include "dcn31/dcn31_resource.h" #include "dcn10/dcn10_ipp.h" #include "dcn30/dcn30_hubbub.h" #include "dcn31/dcn31_hubbub.h" #include "dcn30/dcn30_mpc.h" #include "dcn31/dcn31_hubp.h" #include "irq/dcn315/irq_service_dcn315.h" #include "dcn30/dcn30_dpp.h" #include "dcn31/dcn31_optc.h" #include "dcn20/dcn20_hwseq.h" #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" #include "dcn20/dcn20_dsc.h" #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" #include "dcn31/dcn31_hpo_dp_stream_encoder.h" #include "dcn31/dcn31_hpo_dp_link_encoder.h" #include "dcn31/dcn31_apg.h" #include "dcn31/dcn31_dio_link_encoder.h" #include "dcn31/dcn31_vpg.h" #include "dcn31/dcn31_afmt.h" #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" #include "virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dml/dcn31/dcn31_fpu.h" #include "dcn31/dcn31_dccg.h" #include "dcn10/dcn10_resource.h" #include "dcn31/dcn31_panel_cntl.h" #include "dcn30/dcn30_dwb.h" #include "dcn30/dcn30_mmhubbub.h" #include "dcn/dcn_3_1_5_offset.h" #include "dcn/dcn_3_1_5_sh_mask.h" #include "dpcs/dpcs_4_2_2_offset.h" #include "dpcs/dpcs_4_2_2_sh_mask.h" #define NBIO_BASE__INST0_SEG0 … #define NBIO_BASE__INST0_SEG1 … #define NBIO_BASE__INST0_SEG2 … #define NBIO_BASE__INST0_SEG3 … #define NBIO_BASE__INST0_SEG4 … #define NBIO_BASE__INST0_SEG5 … #define DPCS_BASE__INST0_SEG0 … #define DPCS_BASE__INST0_SEG1 … #define DPCS_BASE__INST0_SEG2 … #define DPCS_BASE__INST0_SEG3 … #define DPCS_BASE__INST0_SEG4 … #define DPCS_BASE__INST0_SEG5 … #define DCN_BASE__INST0_SEG0 … #define DCN_BASE__INST0_SEG1 … #define DCN_BASE__INST0_SEG2 … #define DCN_BASE__INST0_SEG3 … #define DCN_BASE__INST0_SEG4 … #define DCN_BASE__INST0_SEG5 … #define regBIF_BX_PF2_RSMU_INDEX … #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX … #define regBIF_BX_PF2_RSMU_DATA … #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX … #define regBIF_BX2_BIOS_SCRATCH_6 … #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX … #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT … #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK … #define regBIF_BX2_BIOS_SCRATCH_2 … #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX … #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT … #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK … #define regBIF_BX2_BIOS_SCRATCH_3 … #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX … #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT … #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK … #define regDCHUBBUB_DEBUG_CTRL_0 … #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX … #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT … #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK … #include "reg_helper.h" #include "dce/dmub_abm.h" #include "dce/dmub_psr.h" #include "dce/dmub_replay.h" #include "dce/dce_aux.h" #include "dce/dce_i2c.h" #include "dml/dcn30/display_mode_vba_30.h" #include "vm_helper.h" #include "dcn20/dcn20_vmid.h" #include "link_enc_cfg.h" #define DCN3_15_MAX_DET_SIZE … #define DCN3_15_CRB_SEGMENT_SIZE_KB … #define DCN3_15_MAX_DET_SEGS … /* Minimum 3 extra segments need to be in compbuf and claimable to guarantee seamless mpo transitions */ #define MIN_RESERVED_DET_SEGS … enum dcn31_clk_src_array_id { … }; /* begin ********************* * macros to expend register list macro defined in HW object header file */ /* DCN */ #define BASE_INNER(seg) … #define BASE(seg) … #define SR(reg_name) … #define SRI(reg_name, block, id) … #define SRI2(reg_name, block, id) … #define SRIR(var_name, reg_name, block, id) … #define SRII(reg_name, block, id) … #define SRII_MPC_RMU(reg_name, block, id) … #define SRII_DWB(reg_name, temp_name, block, id) … #define SF_DWB2(reg_name, block, id, field_name, post_fix) … #define DCCG_SRII(reg_name, block, id) … #define VUPDATE_SRII(reg_name, block, id) … /* NBIO */ #define NBIO_BASE_INNER(seg) … #define NBIO_BASE(seg) … #define NBIO_SR(reg_name) … static const struct bios_registers bios_regs = …; #define clk_src_regs(index, pllid) … static const struct dce110_clk_src_regs clk_src_regs[] = …; static const struct dce110_clk_src_shift cs_shift = …; static const struct dce110_clk_src_mask cs_mask = …; #define abm_regs(id) … static const struct dce_abm_registers abm_regs[] = …; static const struct dce_abm_shift abm_shift = …; static const struct dce_abm_mask abm_mask = …; #define audio_regs(id) … static const struct dce_audio_registers audio_regs[] = …; #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh) … static const struct dce_audio_shift audio_shift = …; static const struct dce_audio_mask audio_mask = …; #define vpg_regs(id) … static const struct dcn31_vpg_registers vpg_regs[] = …; static const struct dcn31_vpg_shift vpg_shift = …; static const struct dcn31_vpg_mask vpg_mask = …; #define afmt_regs(id) … static const struct dcn31_afmt_registers afmt_regs[] = …; static const struct dcn31_afmt_shift afmt_shift = …; static const struct dcn31_afmt_mask afmt_mask = …; #define apg_regs(id) … static const struct dcn31_apg_registers apg_regs[] = …; static const struct dcn31_apg_shift apg_shift = …; static const struct dcn31_apg_mask apg_mask = …; #define stream_enc_regs(id) … static const struct dcn10_stream_enc_registers stream_enc_regs[] = …; static const struct dcn10_stream_encoder_shift se_shift = …; static const struct dcn10_stream_encoder_mask se_mask = …; #define aux_regs(id) … static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = …; #define hpd_regs(id) … static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = …; #define link_regs(id, phyid) … static const struct dce110_aux_registers_shift aux_shift = …; static const struct dce110_aux_registers_mask aux_mask = …; static const struct dcn10_link_enc_registers link_enc_regs[] = …; static const struct dcn10_link_enc_shift le_shift = …; static const struct dcn10_link_enc_mask le_mask = …; #define hpo_dp_stream_encoder_reg_list(id) … static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = …; static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = …; static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = …; #define hpo_dp_link_encoder_reg_list(id) … static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = …; static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = …; static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = …; #define dpp_regs(id) … static const struct dcn3_dpp_registers dpp_regs[] = …; static const struct dcn3_dpp_shift tf_shift = …; static const struct dcn3_dpp_mask tf_mask = …; #define opp_regs(id) … static const struct dcn20_opp_registers opp_regs[] = …; static const struct dcn20_opp_shift opp_shift = …; static const struct dcn20_opp_mask opp_mask = …; #define aux_engine_regs(id) … static const struct dce110_aux_registers aux_engine_regs[] = …; #define dwbc_regs_dcn3(id) … static const struct dcn30_dwbc_registers dwbc30_regs[] = …; static const struct dcn30_dwbc_shift dwbc30_shift = …; static const struct dcn30_dwbc_mask dwbc30_mask = …; #define mcif_wb_regs_dcn3(id) … static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = …; static const struct dcn30_mmhubbub_shift mcif_wb30_shift = …; static const struct dcn30_mmhubbub_mask mcif_wb30_mask = …; #define dsc_regsDCN20(id) … static const struct dcn20_dsc_registers dsc_regs[] = …; static const struct dcn20_dsc_shift dsc_shift = …; static const struct dcn20_dsc_mask dsc_mask = …; static const struct dcn30_mpc_registers mpc_regs = …; static const struct dcn30_mpc_shift mpc_shift = …; static const struct dcn30_mpc_mask mpc_mask = …; #define optc_regs(id) … static const struct dcn_optc_registers optc_regs[] = …; static const struct dcn_optc_shift optc_shift = …; static const struct dcn_optc_mask optc_mask = …; #define hubp_regs(id) … static const struct dcn_hubp2_registers hubp_regs[] = …; static const struct dcn_hubp2_shift hubp_shift = …; static const struct dcn_hubp2_mask hubp_mask = …; static const struct dcn_hubbub_registers hubbub_reg = …; static const struct dcn_hubbub_shift hubbub_shift = …; static const struct dcn_hubbub_mask hubbub_mask = …; static const struct dccg_registers dccg_regs = …; static const struct dccg_shift dccg_shift = …; static const struct dccg_mask dccg_mask = …; #define SRII2(reg_name_pre, reg_name_post, id) … #define HWSEQ_DCN31_REG_LIST() … static const struct dce_hwseq_registers hwseq_reg = …; #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh) … static const struct dce_hwseq_shift hwseq_shift = …; static const struct dce_hwseq_mask hwseq_mask = …; #define vmid_regs(id) … static const struct dcn_vmid_registers vmid_regs[] = …; static const struct dcn20_vmid_shift vmid_shifts = …; static const struct dcn20_vmid_mask vmid_masks = …; static const struct resource_caps res_cap_dcn31 = …; static const struct dc_plane_cap plane_cap = …; static const struct dc_debug_options debug_defaults_drv = …; static const struct dc_panel_config panel_config_defaults = …; static void dcn31_dpp_destroy(struct dpp **dpp) { … } static struct dpp *dcn31_dpp_create( struct dc_context *ctx, uint32_t inst) { … } static struct output_pixel_processor *dcn31_opp_create( struct dc_context *ctx, uint32_t inst) { … } static struct dce_aux *dcn31_aux_engine_create( struct dc_context *ctx, uint32_t inst) { … } #define i2c_inst_regs(id) … static const struct dce_i2c_registers i2c_hw_regs[] = …; static const struct dce_i2c_shift i2c_shifts = …; static const struct dce_i2c_mask i2c_masks = …; static struct dce_i2c_hw *dcn31_i2c_hw_create( struct dc_context *ctx, uint32_t inst) { … } static struct mpc *dcn31_mpc_create( struct dc_context *ctx, int num_mpcc, int num_rmu) { … } static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) { … } static struct timing_generator *dcn31_timing_generator_create( struct dc_context *ctx, uint32_t instance) { … } static const struct encoder_feature_support link_enc_feature = …; static struct link_encoder *dcn31_link_encoder_create( struct dc_context *ctx, const struct encoder_init_data *enc_init_data) { … } /* Create a minimal link encoder object not associated with a particular * physical connector. * resource_funcs.link_enc_create_minimal */ static struct link_encoder *dcn31_link_enc_create_minimal( struct dc_context *ctx, enum engine_id eng_id) { … } static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) { … } static void read_dce_straps( struct dc_context *ctx, struct resource_straps *straps) { … } static struct audio *dcn31_create_audio( struct dc_context *ctx, unsigned int inst) { … } static struct vpg *dcn31_vpg_create( struct dc_context *ctx, uint32_t inst) { … } static struct afmt *dcn31_afmt_create( struct dc_context *ctx, uint32_t inst) { … } static struct apg *dcn31_apg_create( struct dc_context *ctx, uint32_t inst) { … } static struct stream_encoder *dcn315_stream_encoder_create( enum engine_id eng_id, struct dc_context *ctx) { … } static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( enum engine_id eng_id, struct dc_context *ctx) { … } static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( uint8_t inst, struct dc_context *ctx) { … } static struct dce_hwseq *dcn31_hwseq_create( struct dc_context *ctx) { … } static const struct resource_create_funcs res_create_funcs = …; static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) { … } static struct hubp *dcn31_hubp_create( struct dc_context *ctx, uint32_t inst) { … } static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { … } static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { … } static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { … } static void dcn315_destroy_resource_pool(struct resource_pool **pool) { … } static struct clock_source *dcn31_clock_source_create( struct dc_context *ctx, struct dc_bios *bios, enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) { … } static bool is_dual_plane(enum surface_pixel_format format) { … } static int source_format_to_bpp (enum source_format_class SourcePixelFormat) { … } static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context) { … } static int dcn315_populate_dml_pipes_from_context( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) { … } static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_config) { … } static struct dc_cap_funcs cap_funcs = …; static struct resource_funcs dcn315_res_pool_funcs = …; static bool dcn315_resource_construct( uint8_t num_virtual_links, struct dc *dc, struct dcn315_resource_pool *pool) { … } struct resource_pool *dcn315_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc) { … }
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