// SPDX-License-Identifier: GPL-2.0-only // Copyright (C) 2014-2017 Broadcom /* * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that * supports the chipCommonA GPIO controller. Basic PINCONF such as bias, * pull up/down, slew and drive strength are also supported in this driver. * * Pins from the chipCommonA GPIO can be individually muxed to GPIO function, * through the interaction with the NSP IOMUX controller. */ #include <linux/gpio/driver.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/ioport.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> #include <linux/slab.h> #include "../pinctrl-utils.h" #define NSP_CHIP_A_INT_STATUS … #define NSP_CHIP_A_INT_MASK … #define NSP_GPIO_DATA_IN … #define NSP_GPIO_DATA_OUT … #define NSP_GPIO_OUT_EN … #define NSP_GPIO_INT_POLARITY … #define NSP_GPIO_INT_MASK … #define NSP_GPIO_EVENT … #define NSP_GPIO_EVENT_INT_MASK … #define NSP_GPIO_EVENT_INT_POLARITY … #define NSP_CHIP_A_GPIO_INT_BIT … /* I/O parameters offset for chipcommon A GPIO */ #define NSP_GPIO_DRV_CTRL … #define NSP_GPIO_HYSTERESIS_EN … #define NSP_GPIO_SLEW_RATE_EN … #define NSP_PULL_UP_EN … #define NSP_PULL_DOWN_EN … #define GPIO_DRV_STRENGTH_BITS … /* * nsp GPIO core * * @dev: pointer to device * @base: I/O register base for nsp GPIO controller * @io_ctrl: I/O register base for PINCONF support outside the GPIO block * @gc: GPIO chip * @pctl: pointer to pinctrl_dev * @pctldesc: pinctrl descriptor * @lock: lock to protect access to I/O registers */ struct nsp_gpio { … }; enum base_type { … }; /* * Mapping from PINCONF pins to GPIO pins is 1-to-1 */ static inline unsigned nsp_pin_to_gpio(unsigned pin) { … } /* * nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a * nsp GPIO register * * @nsp_gpio: nsp GPIO device * @base_type: reg base to modify * @reg: register offset * @gpio: GPIO pin * @set: set or clear */ static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address, unsigned int reg, unsigned gpio, bool set) { … } /* * nsp_get_bit - get one bit (corresponding to the GPIO pin) in a * nsp GPIO register */ static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address, unsigned int reg, unsigned gpio) { … } static irqreturn_t nsp_gpio_irq_handler(int irq, void *data) { … } static void nsp_gpio_irq_ack(struct irq_data *d) { … } /* * nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt * * @d: IRQ chip data * @unmask: mask/unmask GPIO interrupt */ static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask) { … } static void nsp_gpio_irq_mask(struct irq_data *d) { … } static void nsp_gpio_irq_unmask(struct irq_data *d) { … } static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type) { … } static const struct irq_chip nsp_gpio_irq_chip = …; static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) { … } static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, int val) { … } static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio) { … } static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) { … } static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio) { … } static int nsp_get_groups_count(struct pinctrl_dev *pctldev) { … } /* * Only one group: "gpio_grp", since this local pinctrl device only performs * GPIO specific PINCONF configurations */ static const char *nsp_get_group_name(struct pinctrl_dev *pctldev, unsigned selector) { … } static const struct pinctrl_ops nsp_pctrl_ops = …; static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u32 slew) { … } static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio, bool pull_up, bool pull_down) { … } static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio, bool *pull_up, bool *pull_down) { … } static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio, u32 strength) { … } static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio, u16 *strength) { … } static int nsp_pin_config_group_get(struct pinctrl_dev *pctldev, unsigned selector, unsigned long *config) { … } static int nsp_pin_config_group_set(struct pinctrl_dev *pctldev, unsigned selector, unsigned long *configs, unsigned num_configs) { … } static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config) { … } static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs, unsigned num_configs) { … } static const struct pinconf_ops nsp_pconf_ops = …; /* * NSP GPIO controller supports some PINCONF related configurations such as * pull up, pull down, slew and drive strength, when the pin is configured * to GPIO. * * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the * local GPIO pins */ static int nsp_gpio_register_pinconf(struct nsp_gpio *chip) { … } static const struct of_device_id nsp_gpio_of_match[] = …; static int nsp_gpio_probe(struct platform_device *pdev) { … } static struct platform_driver nsp_gpio_driver = …; static int __init nsp_gpio_init(void) { … } arch_initcall_sync(nsp_gpio_init);
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