/* SPDX-License-Identifier: GPL-2.0 */ /* * Lochnagar2 register definitions * * Copyright (c) 2017-2018 Cirrus Logic, Inc. and * Cirrus Logic International Semiconductor Ltd. * * Author: Charles Keepax <[email protected]> */ #ifndef LOCHNAGAR2_REGISTERS_H #define LOCHNAGAR2_REGISTERS_H /* Register Addresses */ #define LOCHNAGAR2_CDC_AIF1_CTRL … #define LOCHNAGAR2_CDC_AIF2_CTRL … #define LOCHNAGAR2_CDC_AIF3_CTRL … #define LOCHNAGAR2_DSP_AIF1_CTRL … #define LOCHNAGAR2_DSP_AIF2_CTRL … #define LOCHNAGAR2_PSIA1_CTRL … #define LOCHNAGAR2_PSIA2_CTRL … #define LOCHNAGAR2_GF_AIF3_CTRL … #define LOCHNAGAR2_GF_AIF4_CTRL … #define LOCHNAGAR2_GF_AIF1_CTRL … #define LOCHNAGAR2_GF_AIF2_CTRL … #define LOCHNAGAR2_SPDIF_AIF_CTRL … #define LOCHNAGAR2_USB_AIF1_CTRL … #define LOCHNAGAR2_USB_AIF2_CTRL … #define LOCHNAGAR2_ADAT_AIF_CTRL … #define LOCHNAGAR2_CDC_MCLK1_CTRL … #define LOCHNAGAR2_CDC_MCLK2_CTRL … #define LOCHNAGAR2_DSP_CLKIN_CTRL … #define LOCHNAGAR2_PSIA1_MCLK_CTRL … #define LOCHNAGAR2_PSIA2_MCLK_CTRL … #define LOCHNAGAR2_SPDIF_MCLK_CTRL … #define LOCHNAGAR2_GF_CLKOUT1_CTRL … #define LOCHNAGAR2_GF_CLKOUT2_CTRL … #define LOCHNAGAR2_ADAT_MCLK_CTRL … #define LOCHNAGAR2_SOUNDCARD_MCLK_CTRL … #define LOCHNAGAR2_GPIO_FPGA_GPIO1 … #define LOCHNAGAR2_GPIO_FPGA_GPIO2 … #define LOCHNAGAR2_GPIO_FPGA_GPIO3 … #define LOCHNAGAR2_GPIO_FPGA_GPIO4 … #define LOCHNAGAR2_GPIO_FPGA_GPIO5 … #define LOCHNAGAR2_GPIO_FPGA_GPIO6 … #define LOCHNAGAR2_GPIO_CDC_GPIO1 … #define LOCHNAGAR2_GPIO_CDC_GPIO2 … #define LOCHNAGAR2_GPIO_CDC_GPIO3 … #define LOCHNAGAR2_GPIO_CDC_GPIO4 … #define LOCHNAGAR2_GPIO_CDC_GPIO5 … #define LOCHNAGAR2_GPIO_CDC_GPIO6 … #define LOCHNAGAR2_GPIO_CDC_GPIO7 … #define LOCHNAGAR2_GPIO_CDC_GPIO8 … #define LOCHNAGAR2_GPIO_DSP_GPIO1 … #define LOCHNAGAR2_GPIO_DSP_GPIO2 … #define LOCHNAGAR2_GPIO_DSP_GPIO3 … #define LOCHNAGAR2_GPIO_DSP_GPIO4 … #define LOCHNAGAR2_GPIO_DSP_GPIO5 … #define LOCHNAGAR2_GPIO_DSP_GPIO6 … #define LOCHNAGAR2_GPIO_GF_GPIO2 … #define LOCHNAGAR2_GPIO_GF_GPIO3 … #define LOCHNAGAR2_GPIO_GF_GPIO7 … #define LOCHNAGAR2_GPIO_CDC_AIF1_BCLK … #define LOCHNAGAR2_GPIO_CDC_AIF1_RXDAT … #define LOCHNAGAR2_GPIO_CDC_AIF1_LRCLK … #define LOCHNAGAR2_GPIO_CDC_AIF1_TXDAT … #define LOCHNAGAR2_GPIO_CDC_AIF2_BCLK … #define LOCHNAGAR2_GPIO_CDC_AIF2_RXDAT … #define LOCHNAGAR2_GPIO_CDC_AIF2_LRCLK … #define LOCHNAGAR2_GPIO_CDC_AIF2_TXDAT … #define LOCHNAGAR2_GPIO_CDC_AIF3_BCLK … #define LOCHNAGAR2_GPIO_CDC_AIF3_RXDAT … #define LOCHNAGAR2_GPIO_CDC_AIF3_LRCLK … #define LOCHNAGAR2_GPIO_CDC_AIF3_TXDAT … #define LOCHNAGAR2_GPIO_DSP_AIF1_BCLK … #define LOCHNAGAR2_GPIO_DSP_AIF1_RXDAT … #define LOCHNAGAR2_GPIO_DSP_AIF1_LRCLK … #define LOCHNAGAR2_GPIO_DSP_AIF1_TXDAT … #define LOCHNAGAR2_GPIO_DSP_AIF2_BCLK … #define LOCHNAGAR2_GPIO_DSP_AIF2_RXDAT … #define LOCHNAGAR2_GPIO_DSP_AIF2_LRCLK … #define LOCHNAGAR2_GPIO_DSP_AIF2_TXDAT … #define LOCHNAGAR2_GPIO_PSIA1_BCLK … #define LOCHNAGAR2_GPIO_PSIA1_RXDAT … #define LOCHNAGAR2_GPIO_PSIA1_LRCLK … #define LOCHNAGAR2_GPIO_PSIA1_TXDAT … #define LOCHNAGAR2_GPIO_PSIA2_BCLK … #define LOCHNAGAR2_GPIO_PSIA2_RXDAT … #define LOCHNAGAR2_GPIO_PSIA2_LRCLK … #define LOCHNAGAR2_GPIO_PSIA2_TXDAT … #define LOCHNAGAR2_GPIO_GF_AIF3_BCLK … #define LOCHNAGAR2_GPIO_GF_AIF3_RXDAT … #define LOCHNAGAR2_GPIO_GF_AIF3_LRCLK … #define LOCHNAGAR2_GPIO_GF_AIF3_TXDAT … #define LOCHNAGAR2_GPIO_GF_AIF4_BCLK … #define LOCHNAGAR2_GPIO_GF_AIF4_RXDAT … #define LOCHNAGAR2_GPIO_GF_AIF4_LRCLK … #define LOCHNAGAR2_GPIO_GF_AIF4_TXDAT … #define LOCHNAGAR2_GPIO_GF_AIF1_BCLK … #define LOCHNAGAR2_GPIO_GF_AIF1_RXDAT … #define LOCHNAGAR2_GPIO_GF_AIF1_LRCLK … #define LOCHNAGAR2_GPIO_GF_AIF1_TXDAT … #define LOCHNAGAR2_GPIO_GF_AIF2_BCLK … #define LOCHNAGAR2_GPIO_GF_AIF2_RXDAT … #define LOCHNAGAR2_GPIO_GF_AIF2_LRCLK … #define LOCHNAGAR2_GPIO_GF_AIF2_TXDAT … #define LOCHNAGAR2_GPIO_DSP_UART1_RX … #define LOCHNAGAR2_GPIO_DSP_UART1_TX … #define LOCHNAGAR2_GPIO_DSP_UART2_RX … #define LOCHNAGAR2_GPIO_DSP_UART2_TX … #define LOCHNAGAR2_GPIO_GF_UART2_RX … #define LOCHNAGAR2_GPIO_GF_UART2_TX … #define LOCHNAGAR2_GPIO_USB_UART_RX … #define LOCHNAGAR2_GPIO_CDC_PDMCLK1 … #define LOCHNAGAR2_GPIO_CDC_PDMDAT1 … #define LOCHNAGAR2_GPIO_CDC_PDMCLK2 … #define LOCHNAGAR2_GPIO_CDC_PDMDAT2 … #define LOCHNAGAR2_GPIO_CDC_DMICCLK1 … #define LOCHNAGAR2_GPIO_CDC_DMICDAT1 … #define LOCHNAGAR2_GPIO_CDC_DMICCLK2 … #define LOCHNAGAR2_GPIO_CDC_DMICDAT2 … #define LOCHNAGAR2_GPIO_CDC_DMICCLK3 … #define LOCHNAGAR2_GPIO_CDC_DMICDAT3 … #define LOCHNAGAR2_GPIO_CDC_DMICCLK4 … #define LOCHNAGAR2_GPIO_CDC_DMICDAT4 … #define LOCHNAGAR2_GPIO_DSP_DMICCLK1 … #define LOCHNAGAR2_GPIO_DSP_DMICDAT1 … #define LOCHNAGAR2_GPIO_DSP_DMICCLK2 … #define LOCHNAGAR2_GPIO_DSP_DMICDAT2 … #define LOCHNAGAR2_GPIO_I2C2_SCL … #define LOCHNAGAR2_GPIO_I2C2_SDA … #define LOCHNAGAR2_GPIO_I2C3_SCL … #define LOCHNAGAR2_GPIO_I2C3_SDA … #define LOCHNAGAR2_GPIO_I2C4_SCL … #define LOCHNAGAR2_GPIO_I2C4_SDA … #define LOCHNAGAR2_GPIO_DSP_STANDBY … #define LOCHNAGAR2_GPIO_CDC_MCLK1 … #define LOCHNAGAR2_GPIO_CDC_MCLK2 … #define LOCHNAGAR2_GPIO_DSP_CLKIN … #define LOCHNAGAR2_GPIO_PSIA1_MCLK … #define LOCHNAGAR2_GPIO_PSIA2_MCLK … #define LOCHNAGAR2_GPIO_GF_GPIO1 … #define LOCHNAGAR2_GPIO_GF_GPIO5 … #define LOCHNAGAR2_GPIO_DSP_GPIO20 … #define LOCHNAGAR2_GPIO_CHANNEL1 … #define LOCHNAGAR2_GPIO_CHANNEL2 … #define LOCHNAGAR2_GPIO_CHANNEL3 … #define LOCHNAGAR2_GPIO_CHANNEL4 … #define LOCHNAGAR2_GPIO_CHANNEL5 … #define LOCHNAGAR2_GPIO_CHANNEL6 … #define LOCHNAGAR2_GPIO_CHANNEL7 … #define LOCHNAGAR2_GPIO_CHANNEL8 … #define LOCHNAGAR2_GPIO_CHANNEL9 … #define LOCHNAGAR2_GPIO_CHANNEL10 … #define LOCHNAGAR2_GPIO_CHANNEL11 … #define LOCHNAGAR2_GPIO_CHANNEL12 … #define LOCHNAGAR2_GPIO_CHANNEL13 … #define LOCHNAGAR2_GPIO_CHANNEL14 … #define LOCHNAGAR2_GPIO_CHANNEL15 … #define LOCHNAGAR2_GPIO_CHANNEL16 … #define LOCHNAGAR2_MINICARD_RESETS … #define LOCHNAGAR2_ANALOGUE_PATH_CTRL1 … #define LOCHNAGAR2_ANALOGUE_PATH_CTRL2 … #define LOCHNAGAR2_COMMS_CTRL4 … #define LOCHNAGAR2_SPDIF_CTRL … #define LOCHNAGAR2_IMON_CTRL1 … #define LOCHNAGAR2_IMON_CTRL2 … #define LOCHNAGAR2_IMON_CTRL3 … #define LOCHNAGAR2_IMON_CTRL4 … #define LOCHNAGAR2_IMON_DATA1 … #define LOCHNAGAR2_IMON_DATA2 … #define LOCHNAGAR2_POWER_CTRL … #define LOCHNAGAR2_MICVDD_CTRL1 … #define LOCHNAGAR2_MICVDD_CTRL2 … #define LOCHNAGAR2_VDDCORE_CDC_CTRL1 … #define LOCHNAGAR2_VDDCORE_CDC_CTRL2 … #define LOCHNAGAR2_SOUNDCARD_AIF_CTRL … /* (0x000D-0x001B, 0x0180) CDC_AIF1_CTRL - SOUNCARD_AIF_CTRL */ #define LOCHNAGAR2_AIF_ENA_MASK … #define LOCHNAGAR2_AIF_ENA_SHIFT … #define LOCHNAGAR2_AIF_LRCLK_DIR_MASK … #define LOCHNAGAR2_AIF_LRCLK_DIR_SHIFT … #define LOCHNAGAR2_AIF_BCLK_DIR_MASK … #define LOCHNAGAR2_AIF_BCLK_DIR_SHIFT … #define LOCHNAGAR2_AIF_SRC_MASK … #define LOCHNAGAR2_AIF_SRC_SHIFT … /* (0x001E - 0x0027) CDC_MCLK1_CTRL - SOUNDCARD_MCLK_CTRL */ #define LOCHNAGAR2_CLK_ENA_MASK … #define LOCHNAGAR2_CLK_ENA_SHIFT … #define LOCHNAGAR2_CLK_SRC_MASK … #define LOCHNAGAR2_CLK_SRC_SHIFT … /* (0x0031 - 0x009A) GPIO_FPGA_GPIO1 - GPIO_DSP_GPIO20 */ #define LOCHNAGAR2_GPIO_SRC_MASK … #define LOCHNAGAR2_GPIO_SRC_SHIFT … /* (0x00B9 - 0x00C8) GPIO_CHANNEL1 - GPIO_CHANNEL16 */ #define LOCHNAGAR2_GPIO_CHANNEL_STS_MASK … #define LOCHNAGAR2_GPIO_CHANNEL_STS_SHIFT … #define LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK … #define LOCHNAGAR2_GPIO_CHANNEL_SRC_SHIFT … /* (0x00DF) MINICARD_RESETS */ #define LOCHNAGAR2_DSP_RESET_MASK … #define LOCHNAGAR2_DSP_RESET_SHIFT … #define LOCHNAGAR2_CDC_RESET_MASK … #define LOCHNAGAR2_CDC_RESET_SHIFT … /* (0x00E3) ANALOGUE_PATH_CTRL1 */ #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_MASK … #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_SHIFT … #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_MASK … #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_SHIFT … /* (0x00E4) ANALOGUE_PATH_CTRL2 */ #define LOCHNAGAR2_P2_INPUT_BIAS_ENA_MASK … #define LOCHNAGAR2_P2_INPUT_BIAS_ENA_SHIFT … #define LOCHNAGAR2_P1_INPUT_BIAS_ENA_MASK … #define LOCHNAGAR2_P1_INPUT_BIAS_ENA_SHIFT … #define LOCHNAGAR2_P2_MICBIAS_SRC_MASK … #define LOCHNAGAR2_P2_MICBIAS_SRC_SHIFT … #define LOCHNAGAR2_P1_MICBIAS_SRC_MASK … #define LOCHNAGAR2_P1_MICBIAS_SRC_SHIFT … /* (0x00F0) COMMS_CTRL4 */ #define LOCHNAGAR2_CDC_CIF1MODE_MASK … #define LOCHNAGAR2_CDC_CIF1MODE_SHIFT … /* (0x00FE) SPDIF_CTRL */ #define LOCHNAGAR2_SPDIF_HWMODE_MASK … #define LOCHNAGAR2_SPDIF_HWMODE_SHIFT … #define LOCHNAGAR2_SPDIF_RESET_MASK … #define LOCHNAGAR2_SPDIF_RESET_SHIFT … /* (0x0108) IMON_CTRL1 */ #define LOCHNAGAR2_IMON_ENA_MASK … #define LOCHNAGAR2_IMON_ENA_SHIFT … #define LOCHNAGAR2_IMON_MEASURED_CHANNELS_MASK … #define LOCHNAGAR2_IMON_MEASURED_CHANNELS_SHIFT … #define LOCHNAGAR2_IMON_MODE_SEL_MASK … #define LOCHNAGAR2_IMON_MODE_SEL_SHIFT … /* (0x0109) IMON_CTRL2 */ #define LOCHNAGAR2_IMON_FSR_MASK … #define LOCHNAGAR2_IMON_FSR_SHIFT … /* (0x010A) IMON_CTRL3 */ #define LOCHNAGAR2_IMON_DONE_MASK … #define LOCHNAGAR2_IMON_DONE_SHIFT … #define LOCHNAGAR2_IMON_CONFIGURE_MASK … #define LOCHNAGAR2_IMON_CONFIGURE_SHIFT … #define LOCHNAGAR2_IMON_MEASURE_MASK … #define LOCHNAGAR2_IMON_MEASURE_SHIFT … /* (0x010B) IMON_CTRL4 */ #define LOCHNAGAR2_IMON_DATA_REQ_MASK … #define LOCHNAGAR2_IMON_DATA_REQ_SHIFT … #define LOCHNAGAR2_IMON_CH_SEL_MASK … #define LOCHNAGAR2_IMON_CH_SEL_SHIFT … #define LOCHNAGAR2_IMON_DATA_RDY_MASK … #define LOCHNAGAR2_IMON_DATA_RDY_SHIFT … #define LOCHNAGAR2_IMON_CH_SRC_MASK … #define LOCHNAGAR2_IMON_CH_SRC_SHIFT … /* (0x010C, 0x010D) IMON_DATA1, IMON_DATA2 */ #define LOCHNAGAR2_IMON_DATA_MASK … #define LOCHNAGAR2_IMON_DATA_SHIFT … /* (0x0116) POWER_CTRL */ #define LOCHNAGAR2_PWR_ENA_MASK … #define LOCHNAGAR2_PWR_ENA_SHIFT … /* (0x0119) MICVDD_CTRL1 */ #define LOCHNAGAR2_MICVDD_REG_ENA_MASK … #define LOCHNAGAR2_MICVDD_REG_ENA_SHIFT … /* (0x011B) MICVDD_CTRL2 */ #define LOCHNAGAR2_MICVDD_VSEL_MASK … #define LOCHNAGAR2_MICVDD_VSEL_SHIFT … /* (0x011E) VDDCORE_CDC_CTRL1 */ #define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_MASK … #define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_SHIFT … /* (0x0120) VDDCORE_CDC_CTRL2 */ #define LOCHNAGAR2_VDDCORE_CDC_VSEL_MASK … #define LOCHNAGAR2_VDDCORE_CDC_VSEL_SHIFT … #endif
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