/* SPDX-License-Identifier: GPL-2.0 */ /* * cs42l43 register definitions * * Copyright (c) 2022-2023 Cirrus Logic, Inc. and * Cirrus Logic International Semiconductor Ltd. */ #ifndef CS42L43_CORE_REGS_H #define CS42L43_CORE_REGS_H /* Registers */ #define CS42L43_GEN_INT_STAT_1 … #define CS42L43_GEN_INT_MASK_1 … #define CS42L43_DEVID … #define CS42L43_REVID … #define CS42L43_RELID … #define CS42L43_SFT_RESET … #define CS42L43_DRV_CTRL1 … #define CS42L43_DRV_CTRL3 … #define CS42L43_DRV_CTRL4 … #define CS42L43_DRV_CTRL_5 … #define CS42L43_GPIO_CTRL1 … #define CS42L43_GPIO_CTRL2 … #define CS42L43_GPIO_STS … #define CS42L43_GPIO_FN_SEL … #define CS42L43_MCLK_SRC_SEL … #define CS42L43_CCM_BLK_CLK_CONTROL … #define CS42L43_SAMPLE_RATE1 … #define CS42L43_SAMPLE_RATE2 … #define CS42L43_SAMPLE_RATE3 … #define CS42L43_SAMPLE_RATE4 … #define CS42L43_PLL_CONTROL … #define CS42L43_FS_SELECT1 … #define CS42L43_FS_SELECT2 … #define CS42L43_FS_SELECT3 … #define CS42L43_FS_SELECT4 … #define CS42L43_PDM_CONTROL … #define CS42L43_ASP_CLK_CONFIG1 … #define CS42L43_ASP_CLK_CONFIG2 … #define CS42L43_OSC_DIV_SEL … #define CS42L43_ADC_B_CTRL1 … #define CS42L43_ADC_B_CTRL2 … #define CS42L43_DECIM_HPF_WNF_CTRL1 … #define CS42L43_DECIM_HPF_WNF_CTRL2 … #define CS42L43_DECIM_HPF_WNF_CTRL3 … #define CS42L43_DECIM_HPF_WNF_CTRL4 … #define CS42L43_DMIC_PDM_CTRL … #define CS42L43_DECIM_VOL_CTRL_CH1_CH2 … #define CS42L43_DECIM_VOL_CTRL_CH3_CH4 … #define CS42L43_DECIM_VOL_CTRL_UPDATE … #define CS42L43_INTP_VOLUME_CTRL1 … #define CS42L43_INTP_VOLUME_CTRL2 … #define CS42L43_AMP1_2_VOL_RAMP … #define CS42L43_ASP_CTRL … #define CS42L43_ASP_FSYNC_CTRL1 … #define CS42L43_ASP_FSYNC_CTRL2 … #define CS42L43_ASP_FSYNC_CTRL3 … #define CS42L43_ASP_FSYNC_CTRL4 … #define CS42L43_ASP_DATA_CTRL … #define CS42L43_ASP_RX_EN … #define CS42L43_ASP_TX_EN … #define CS42L43_ASP_RX_CH1_CTRL … #define CS42L43_ASP_RX_CH2_CTRL … #define CS42L43_ASP_RX_CH3_CTRL … #define CS42L43_ASP_RX_CH4_CTRL … #define CS42L43_ASP_RX_CH5_CTRL … #define CS42L43_ASP_RX_CH6_CTRL … #define CS42L43_ASP_TX_CH1_CTRL … #define CS42L43_ASP_TX_CH2_CTRL … #define CS42L43_ASP_TX_CH3_CTRL … #define CS42L43_ASP_TX_CH4_CTRL … #define CS42L43_ASP_TX_CH5_CTRL … #define CS42L43_ASP_TX_CH6_CTRL … #define CS42L43_OTP_REVISION_ID … #define CS42L43_ASPTX1_INPUT … #define CS42L43_ASPTX2_INPUT … #define CS42L43_ASPTX3_INPUT … #define CS42L43_ASPTX4_INPUT … #define CS42L43_ASPTX5_INPUT … #define CS42L43_ASPTX6_INPUT … #define CS42L43_SWIRE_DP1_CH1_INPUT … #define CS42L43_SWIRE_DP1_CH2_INPUT … #define CS42L43_SWIRE_DP1_CH3_INPUT … #define CS42L43_SWIRE_DP1_CH4_INPUT … #define CS42L43_SWIRE_DP2_CH1_INPUT … #define CS42L43_SWIRE_DP2_CH2_INPUT … #define CS42L43_SWIRE_DP3_CH1_INPUT … #define CS42L43_SWIRE_DP3_CH2_INPUT … #define CS42L43_SWIRE_DP4_CH1_INPUT … #define CS42L43_SWIRE_DP4_CH2_INPUT … #define CS42L43_ASRC_INT1_INPUT1 … #define CS42L43_ASRC_INT2_INPUT1 … #define CS42L43_ASRC_INT3_INPUT1 … #define CS42L43_ASRC_INT4_INPUT1 … #define CS42L43_ASRC_DEC1_INPUT1 … #define CS42L43_ASRC_DEC2_INPUT1 … #define CS42L43_ASRC_DEC3_INPUT1 … #define CS42L43_ASRC_DEC4_INPUT1 … #define CS42L43_ISRC1INT1_INPUT1 … #define CS42L43_ISRC1INT2_INPUT1 … #define CS42L43_ISRC1DEC1_INPUT1 … #define CS42L43_ISRC1DEC2_INPUT1 … #define CS42L43_ISRC2INT1_INPUT1 … #define CS42L43_ISRC2INT2_INPUT1 … #define CS42L43_ISRC2DEC1_INPUT1 … #define CS42L43_ISRC2DEC2_INPUT1 … #define CS42L43_EQ1MIX_INPUT1 … #define CS42L43_EQ1MIX_INPUT2 … #define CS42L43_EQ1MIX_INPUT3 … #define CS42L43_EQ1MIX_INPUT4 … #define CS42L43_EQ2MIX_INPUT1 … #define CS42L43_EQ2MIX_INPUT2 … #define CS42L43_EQ2MIX_INPUT3 … #define CS42L43_EQ2MIX_INPUT4 … #define CS42L43_SPDIF1_INPUT1 … #define CS42L43_SPDIF2_INPUT1 … #define CS42L43_AMP1MIX_INPUT1 … #define CS42L43_AMP1MIX_INPUT2 … #define CS42L43_AMP1MIX_INPUT3 … #define CS42L43_AMP1MIX_INPUT4 … #define CS42L43_AMP2MIX_INPUT1 … #define CS42L43_AMP2MIX_INPUT2 … #define CS42L43_AMP2MIX_INPUT3 … #define CS42L43_AMP2MIX_INPUT4 … #define CS42L43_AMP3MIX_INPUT1 … #define CS42L43_AMP3MIX_INPUT2 … #define CS42L43_AMP3MIX_INPUT3 … #define CS42L43_AMP3MIX_INPUT4 … #define CS42L43_AMP4MIX_INPUT1 … #define CS42L43_AMP4MIX_INPUT2 … #define CS42L43_AMP4MIX_INPUT3 … #define CS42L43_AMP4MIX_INPUT4 … #define CS42L43_ASRC_INT_ENABLES … #define CS42L43_ASRC_DEC_ENABLES … #define CS42L43_PDNCNTL … #define CS42L43_RINGSENSE_DEB_CTRL … #define CS42L43_TIPSENSE_DEB_CTRL … #define CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS … #define CS42L43_HS2 … #define CS42L43_HS_STAT … #define CS42L43_MCU_SW_INTERRUPT … #define CS42L43_STEREO_MIC_CTRL … #define CS42L43_STEREO_MIC_CLAMP_CTRL … #define CS42L43_BLOCK_EN2 … #define CS42L43_BLOCK_EN3 … #define CS42L43_BLOCK_EN4 … #define CS42L43_BLOCK_EN5 … #define CS42L43_BLOCK_EN6 … #define CS42L43_BLOCK_EN7 … #define CS42L43_BLOCK_EN8 … #define CS42L43_BLOCK_EN9 … #define CS42L43_BLOCK_EN10 … #define CS42L43_BLOCK_EN11 … #define CS42L43_TONE_CH1_CTRL … #define CS42L43_TONE_CH2_CTRL … #define CS42L43_MIC_DETECT_CONTROL_1 … #define CS42L43_DETECT_STATUS_1 … #define CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL … #define CS42L43_MIC_DETECT_CONTROL_ANDROID … #define CS42L43_ISRC1_CTRL … #define CS42L43_ISRC2_CTRL … #define CS42L43_CTRL_REG … #define CS42L43_FDIV_FRAC … #define CS42L43_CAL_RATIO … #define CS42L43_SPI_CLK_CONFIG1 … #define CS42L43_SPI_CONFIG1 … #define CS42L43_SPI_CONFIG2 … #define CS42L43_SPI_CONFIG3 … #define CS42L43_SPI_CONFIG4 … #define CS42L43_SPI_STATUS1 … #define CS42L43_SPI_STATUS2 … #define CS42L43_TRAN_CONFIG1 … #define CS42L43_TRAN_CONFIG2 … #define CS42L43_TRAN_CONFIG3 … #define CS42L43_TRAN_CONFIG4 … #define CS42L43_TRAN_CONFIG5 … #define CS42L43_TRAN_CONFIG6 … #define CS42L43_TRAN_CONFIG7 … #define CS42L43_TRAN_CONFIG8 … #define CS42L43_TRAN_STATUS1 … #define CS42L43_TRAN_STATUS2 … #define CS42L43_TRAN_STATUS3 … #define CS42L43_TX_DATA … #define CS42L43_RX_DATA … #define CS42L43_DACCNFG1 … #define CS42L43_DACCNFG2 … #define CS42L43_HPPATHVOL … #define CS42L43_PGAVOL … #define CS42L43_LOADDETRESULTS … #define CS42L43_LOADDETENA … #define CS42L43_CTRL … #define CS42L43_COEFF_DATA_IN0 … #define CS42L43_COEFF_RD_WR0 … #define CS42L43_INIT_DONE0 … #define CS42L43_START_EQZ0 … #define CS42L43_MUTE_EQ_IN0 … #define CS42L43_DECIM_INT … #define CS42L43_EQ_INT … #define CS42L43_ASP_INT … #define CS42L43_PLL_INT … #define CS42L43_SOFT_INT … #define CS42L43_SWIRE_INT … #define CS42L43_MSM_INT … #define CS42L43_ACC_DET_INT … #define CS42L43_I2C_TGT_INT … #define CS42L43_SPI_MSTR_INT … #define CS42L43_SW_TO_SPI_BRIDGE_INT … #define CS42L43_OTP_INT … #define CS42L43_CLASS_D_AMP_INT … #define CS42L43_GPIO_INT … #define CS42L43_ASRC_INT … #define CS42L43_HPOUT_INT … #define CS42L43_DECIM_MASK … #define CS42L43_EQ_MIX_MASK … #define CS42L43_ASP_MASK … #define CS42L43_PLL_MASK … #define CS42L43_SOFT_MASK … #define CS42L43_SWIRE_MASK … #define CS42L43_MSM_MASK … #define CS42L43_ACC_DET_MASK … #define CS42L43_I2C_TGT_MASK … #define CS42L43_SPI_MSTR_MASK … #define CS42L43_SW_TO_SPI_BRIDGE_MASK … #define CS42L43_OTP_MASK … #define CS42L43_CLASS_D_AMP_MASK … #define CS42L43_GPIO_INT_MASK … #define CS42L43_ASRC_MASK … #define CS42L43_HPOUT_MASK … #define CS42L43_DECIM_INT_SHADOW … #define CS42L43_EQ_MIX_INT_SHADOW … #define CS42L43_ASP_INT_SHADOW … #define CS42L43_PLL_INT_SHADOW … #define CS42L43_SOFT_INT_SHADOW … #define CS42L43_SWIRE_INT_SHADOW … #define CS42L43_MSM_INT_SHADOW … #define CS42L43_ACC_DET_INT_SHADOW … #define CS42L43_I2C_TGT_INT_SHADOW … #define CS42L43_SPI_MSTR_INT_SHADOW … #define CS42L43_SW_TO_SPI_BRIDGE_SHADOW … #define CS42L43_OTP_INT_SHADOW … #define CS42L43_CLASS_D_AMP_INT_SHADOW … #define CS42L43_GPIO_SHADOW … #define CS42L43_ASRC_SHADOW … #define CS42L43_HP_OUT_SHADOW … #define CS42L43_BOOT_CONTROL … #define CS42L43_BLOCK_EN … #define CS42L43_SHUTTER_CONTROL … #define CS42L43_MCU_SW_REV … #define CS42L43_PATCH_START_ADDR … #define CS42L43_NEED_CONFIGS … #define CS42L43_BOOT_STATUS … #define CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS … #define CS42L43_FW_MISSION_CTRL_NEED_CONFIGS … #define CS42L43_FW_MISSION_CTRL_HAVE_CONFIGS … #define CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION … #define CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG … #define CS42L43_MCU_RAM_MAX … /* CS42L43_DEVID */ #define CS42L43_DEVID_VAL … /* CS42L43_GEN_INT_STAT_1 */ #define CS42L43_INT_STAT_GEN1_MASK … #define CS42L43_INT_STAT_GEN1_SHIFT … /* CS42L43_SFT_RESET */ #define CS42L43_SFT_RESET_MASK … #define CS42L43_SFT_RESET_SHIFT … #define CS42L43_SFT_RESET_VAL … /* CS42L43_DRV_CTRL1 */ #define CS42L43_ASP_DOUT_DRV_MASK … #define CS42L43_ASP_DOUT_DRV_SHIFT … #define CS42L43_ASP_FSYNC_DRV_MASK … #define CS42L43_ASP_FSYNC_DRV_SHIFT … #define CS42L43_ASP_BCLK_DRV_MASK … #define CS42L43_ASP_BCLK_DRV_SHIFT … /* CS42L43_DRV_CTRL3 */ #define CS42L43_I2C_ADDR_DRV_MASK … #define CS42L43_I2C_ADDR_DRV_SHIFT … #define CS42L43_I2C_SDA_DRV_MASK … #define CS42L43_I2C_SDA_DRV_SHIFT … #define CS42L43_PDMOUT2_CLK_DRV_MASK … #define CS42L43_PDMOUT2_CLK_DRV_SHIFT … #define CS42L43_PDMOUT2_DATA_DRV_MASK … #define CS42L43_PDMOUT2_DATA_DRV_SHIFT … #define CS42L43_PDMOUT1_CLK_DRV_MASK … #define CS42L43_PDMOUT1_CLK_DRV_SHIFT … #define CS42L43_PDMOUT1_DATA_DRV_MASK … #define CS42L43_PDMOUT1_DATA_DRV_SHIFT … #define CS42L43_SPI_MISO_DRV_MASK … #define CS42L43_SPI_MISO_DRV_SHIFT … /* CS42L43_DRV_CTRL4 */ #define CS42L43_GPIO3_DRV_MASK … #define CS42L43_GPIO3_DRV_SHIFT … #define CS42L43_GPIO2_DRV_MASK … #define CS42L43_GPIO2_DRV_SHIFT … #define CS42L43_GPIO1_DRV_MASK … #define CS42L43_GPIO1_DRV_SHIFT … /* CS42L43_DRV_CTRL_5 */ #define CS42L43_I2C_SCL_DRV_MASK … #define CS42L43_I2C_SCL_DRV_SHIFT … #define CS42L43_SPI_SCK_DRV_MASK … #define CS42L43_SPI_SCK_DRV_SHIFT … #define CS42L43_SPI_MOSI_DRV_MASK … #define CS42L43_SPI_MOSI_DRV_SHIFT … #define CS42L43_SPI_SSB_DRV_MASK … #define CS42L43_SPI_SSB_DRV_SHIFT … #define CS42L43_ASP_DIN_DRV_MASK … #define CS42L43_ASP_DIN_DRV_SHIFT … /* CS42L43_GPIO_CTRL1 */ #define CS42L43_GPIO3_POL_MASK … #define CS42L43_GPIO3_POL_SHIFT … #define CS42L43_GPIO2_POL_MASK … #define CS42L43_GPIO2_POL_SHIFT … #define CS42L43_GPIO1_POL_MASK … #define CS42L43_GPIO1_POL_SHIFT … #define CS42L43_GPIO3_LVL_MASK … #define CS42L43_GPIO3_LVL_SHIFT … #define CS42L43_GPIO2_LVL_MASK … #define CS42L43_GPIO2_LVL_SHIFT … #define CS42L43_GPIO1_LVL_MASK … #define CS42L43_GPIO1_LVL_SHIFT … #define CS42L43_GPIO3_DIR_MASK … #define CS42L43_GPIO3_DIR_SHIFT … #define CS42L43_GPIO2_DIR_MASK … #define CS42L43_GPIO2_DIR_SHIFT … #define CS42L43_GPIO1_DIR_MASK … #define CS42L43_GPIO1_DIR_SHIFT … /* CS42L43_GPIO_CTRL2 */ #define CS42L43_GPIO3_DEGLITCH_BYP_MASK … #define CS42L43_GPIO3_DEGLITCH_BYP_SHIFT … #define CS42L43_GPIO2_DEGLITCH_BYP_MASK … #define CS42L43_GPIO2_DEGLITCH_BYP_SHIFT … #define CS42L43_GPIO1_DEGLITCH_BYP_MASK … #define CS42L43_GPIO1_DEGLITCH_BYP_SHIFT … /* CS42L43_GPIO_STS */ #define CS42L43_GPIO3_STS_MASK … #define CS42L43_GPIO3_STS_SHIFT … #define CS42L43_GPIO2_STS_MASK … #define CS42L43_GPIO2_STS_SHIFT … #define CS42L43_GPIO1_STS_MASK … #define CS42L43_GPIO1_STS_SHIFT … /* CS42L43_GPIO_FN_SEL */ #define CS42L43_GPIO3_FN_SEL_MASK … #define CS42L43_GPIO3_FN_SEL_SHIFT … #define CS42L43_GPIO1_FN_SEL_MASK … #define CS42L43_GPIO1_FN_SEL_SHIFT … /* CS42L43_MCLK_SRC_SEL */ #define CS42L43_OSC_PLL_MCLK_SEL_MASK … #define CS42L43_OSC_PLL_MCLK_SEL_SHIFT … /* CS42L43_SAMPLE_RATE1..CS42L43_SAMPLE_RATE4 */ #define CS42L43_SAMPLE_RATE_MASK … #define CS42L43_SAMPLE_RATE_SHIFT … /* CS42L43_PLL_CONTROL */ #define CS42L43_PLL_REFCLK_EN_MASK … #define CS42L43_PLL_REFCLK_EN_SHIFT … #define CS42L43_PLL_REFCLK_DIV_MASK … #define CS42L43_PLL_REFCLK_DIV_SHIFT … #define CS42L43_PLL_REFCLK_SRC_MASK … #define CS42L43_PLL_REFCLK_SRC_SHIFT … /* CS42L43_FS_SELECT1 */ #define CS42L43_ASP_RATE_MASK … #define CS42L43_ASP_RATE_SHIFT … /* CS42L43_FS_SELECT2 */ #define CS42L43_ASRC_DEC_OUT_RATE_MASK … #define CS42L43_ASRC_DEC_OUT_RATE_SHIFT … #define CS42L43_ASRC_INT_OUT_RATE_MASK … #define CS42L43_ASRC_INT_OUT_RATE_SHIFT … #define CS42L43_ASRC_DEC_IN_RATE_MASK … #define CS42L43_ASRC_DEC_IN_RATE_SHIFT … #define CS42L43_ASRC_INT_IN_RATE_MASK … #define CS42L43_ASRC_INT_IN_RATE_SHIFT … /* CS42L43_FS_SELECT3 */ #define CS42L43_HPOUT_RATE_MASK … #define CS42L43_HPOUT_RATE_SHIFT … #define CS42L43_EQZ_RATE_MASK … #define CS42L43_EQZ_RATE_SHIFT … #define CS42L43_DIAGGEN_RATE_MASK … #define CS42L43_DIAGGEN_RATE_SHIFT … #define CS42L43_DECIM_CH4_RATE_MASK … #define CS42L43_DECIM_CH4_RATE_SHIFT … #define CS42L43_DECIM_CH3_RATE_MASK … #define CS42L43_DECIM_CH3_RATE_SHIFT … #define CS42L43_DECIM_CH2_RATE_MASK … #define CS42L43_DECIM_CH2_RATE_SHIFT … #define CS42L43_DECIM_CH1_RATE_MASK … #define CS42L43_DECIM_CH1_RATE_SHIFT … #define CS42L43_AMP1_2_RATE_MASK … #define CS42L43_AMP1_2_RATE_SHIFT … /* CS42L43_FS_SELECT4 */ #define CS42L43_SW_DP7_RATE_MASK … #define CS42L43_SW_DP7_RATE_SHIFT … #define CS42L43_SW_DP6_RATE_MASK … #define CS42L43_SW_DP6_RATE_SHIFT … #define CS42L43_SPDIF_RATE_MASK … #define CS42L43_SPDIF_RATE_SHIFT … #define CS42L43_SW_DP5_RATE_MASK … #define CS42L43_SW_DP5_RATE_SHIFT … #define CS42L43_SW_DP4_RATE_MASK … #define CS42L43_SW_DP4_RATE_SHIFT … #define CS42L43_SW_DP3_RATE_MASK … #define CS42L43_SW_DP3_RATE_SHIFT … #define CS42L43_SW_DP2_RATE_MASK … #define CS42L43_SW_DP2_RATE_SHIFT … #define CS42L43_SW_DP1_RATE_MASK … #define CS42L43_SW_DP1_RATE_SHIFT … #define CS42L43_ISRC2_LOW_RATE_MASK … #define CS42L43_ISRC2_LOW_RATE_SHIFT … #define CS42L43_ISRC2_HIGH_RATE_MASK … #define CS42L43_ISRC2_HIGH_RATE_SHIFT … #define CS42L43_ISRC1_LOW_RATE_MASK … #define CS42L43_ISRC1_LOW_RATE_SHIFT … #define CS42L43_ISRC1_HIGH_RATE_MASK … #define CS42L43_ISRC1_HIGH_RATE_SHIFT … /* CS42L43_PDM_CONTROL */ #define CS42L43_PDM2_CLK_DIV_MASK … #define CS42L43_PDM2_CLK_DIV_SHIFT … #define CS42L43_PDM1_CLK_DIV_MASK … #define CS42L43_PDM1_CLK_DIV_SHIFT … /* CS42L43_ASP_CLK_CONFIG1 */ #define CS42L43_ASP_BCLK_N_MASK … #define CS42L43_ASP_BCLK_N_SHIFT … #define CS42L43_ASP_BCLK_M_MASK … #define CS42L43_ASP_BCLK_M_SHIFT … /* CS42L43_ASP_CLK_CONFIG2 */ #define CS42L43_ASP_MASTER_MODE_MASK … #define CS42L43_ASP_MASTER_MODE_SHIFT … #define CS42L43_ASP_BCLK_INV_MASK … #define CS42L43_ASP_BCLK_INV_SHIFT … /* CS42L43_OSC_DIV_SEL */ #define CS42L43_OSC_DIV2_EN_MASK … #define CS42L43_OSC_DIV2_EN_SHIFT … /* CS42L43_ADC_B_CTRL1..CS42L43_ADC_B_CTRL1 */ #define CS42L43_PGA_WIDESWING_MODE_EN_MASK … #define CS42L43_PGA_WIDESWING_MODE_EN_SHIFT … #define CS42L43_ADC_AIN_SEL_MASK … #define CS42L43_ADC_AIN_SEL_SHIFT … #define CS42L43_ADC_PGA_GAIN_MASK … #define CS42L43_ADC_PGA_GAIN_SHIFT … /* CS42L43_DECIM_HPF_WNF_CTRL1..CS42L43_DECIM_HPF_WNF_CTRL4 */ #define CS42L43_DECIM_WNF_CF_MASK … #define CS42L43_DECIM_WNF_CF_SHIFT … #define CS42L43_DECIM_WNF_EN_MASK … #define CS42L43_DECIM_WNF_EN_SHIFT … #define CS42L43_DECIM_HPF_CF_MASK … #define CS42L43_DECIM_HPF_CF_SHIFT … #define CS42L43_DECIM_HPF_EN_MASK … #define CS42L43_DECIM_HPF_EN_SHIFT … /* CS42L43_DMIC_PDM_CTRL */ #define CS42L43_PDM2R_INV_MASK … #define CS42L43_PDM2R_INV_SHIFT … #define CS42L43_PDM2L_INV_MASK … #define CS42L43_PDM2L_INV_SHIFT … #define CS42L43_PDM1R_INV_MASK … #define CS42L43_PDM1R_INV_SHIFT … #define CS42L43_PDM1L_INV_MASK … #define CS42L43_PDM1L_INV_SHIFT … /* CS42L43_DECIM_VOL_CTRL_CH1_CH2 */ #define CS42L43_DECIM2_MUTE_MASK … #define CS42L43_DECIM2_MUTE_SHIFT … #define CS42L43_DECIM2_VOL_MASK … #define CS42L43_DECIM2_VOL_SHIFT … #define CS42L43_DECIM2_VD_RAMP_MASK … #define CS42L43_DECIM2_VD_RAMP_SHIFT … #define CS42L43_DECIM2_VI_RAMP_MASK … #define CS42L43_DECIM2_VI_RAMP_SHIFT … #define CS42L43_DECIM1_MUTE_MASK … #define CS42L43_DECIM1_MUTE_SHIFT … #define CS42L43_DECIM1_VOL_MASK … #define CS42L43_DECIM1_VOL_SHIFT … #define CS42L43_DECIM1_VD_RAMP_MASK … #define CS42L43_DECIM1_VD_RAMP_SHIFT … #define CS42L43_DECIM1_VI_RAMP_MASK … #define CS42L43_DECIM1_VI_RAMP_SHIFT … /* CS42L43_DECIM_VOL_CTRL_CH3_CH4 */ #define CS42L43_DECIM4_MUTE_MASK … #define CS42L43_DECIM4_MUTE_SHIFT … #define CS42L43_DECIM4_VOL_MASK … #define CS42L43_DECIM4_VOL_SHIFT … #define CS42L43_DECIM4_VD_RAMP_MASK … #define CS42L43_DECIM4_VD_RAMP_SHIFT … #define CS42L43_DECIM4_VI_RAMP_MASK … #define CS42L43_DECIM4_VI_RAMP_SHIFT … #define CS42L43_DECIM3_MUTE_MASK … #define CS42L43_DECIM3_MUTE_SHIFT … #define CS42L43_DECIM3_VOL_MASK … #define CS42L43_DECIM3_VOL_SHIFT … #define CS42L43_DECIM3_VD_RAMP_MASK … #define CS42L43_DECIM3_VD_RAMP_SHIFT … #define CS42L43_DECIM3_VI_RAMP_MASK … #define CS42L43_DECIM3_VI_RAMP_SHIFT … /* CS42L43_DECIM_VOL_CTRL_UPDATE */ #define CS42L43_DECIM4_VOL_UPDATE_MASK … #define CS42L43_DECIM4_VOL_UPDATE_SHIFT … #define CS42L43_DECIM3_VOL_UPDATE_MASK … #define CS42L43_DECIM3_VOL_UPDATE_SHIFT … #define CS42L43_DECIM2_VOL_UPDATE_MASK … #define CS42L43_DECIM2_VOL_UPDATE_SHIFT … #define CS42L43_DECIM1_VOL_UPDATE_MASK … #define CS42L43_DECIM1_VOL_UPDATE_SHIFT … /* CS42L43_INTP_VOLUME_CTRL1..CS42L43_INTP_VOLUME_CTRL2 */ #define CS42L43_AMP1_2_VU_MASK … #define CS42L43_AMP1_2_VU_SHIFT … #define CS42L43_AMP_MUTE_MASK … #define CS42L43_AMP_MUTE_SHIFT … #define CS42L43_AMP_VOL_MASK … #define CS42L43_AMP_VOL_SHIFT … /* CS42L43_AMP1_2_VOL_RAMP */ #define CS42L43_AMP1_2_VD_RAMP_MASK … #define CS42L43_AMP1_2_VD_RAMP_SHIFT … #define CS42L43_AMP1_2_VI_RAMP_MASK … #define CS42L43_AMP1_2_VI_RAMP_SHIFT … /* CS42L43_ASP_CTRL */ #define CS42L43_ASP_FSYNC_MODE_MASK … #define CS42L43_ASP_FSYNC_MODE_SHIFT … #define CS42L43_ASP_BCLK_EN_MASK … #define CS42L43_ASP_BCLK_EN_SHIFT … #define CS42L43_ASP_FSYNC_EN_MASK … #define CS42L43_ASP_FSYNC_EN_SHIFT … /* CS42L43_ASP_FSYNC_CTRL1 */ #define CS42L43_ASP_FSYNC_M_MASK … #define CS42L43_ASP_FSYNC_M_SHIFT … /* CS42L43_ASP_FSYNC_CTRL3 */ #define CS42L43_ASP_FSYNC_IN_INV_MASK … #define CS42L43_ASP_FSYNC_IN_INV_SHIFT … #define CS42L43_ASP_FSYNC_OUT_INV_MASK … #define CS42L43_ASP_FSYNC_OUT_INV_SHIFT … /* CS42L43_ASP_FSYNC_CTRL4 */ #define CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK … #define CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT … /* CS42L43_ASP_DATA_CTRL */ #define CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK … #define CS42L43_ASP_FSYNC_FRAME_START_PHASE_SHIFT … #define CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK … #define CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT … /* CS42L43_ASP_RX_EN */ #define CS42L43_ASP_RX_CH6_EN_MASK … #define CS42L43_ASP_RX_CH6_EN_SHIFT … #define CS42L43_ASP_RX_CH5_EN_MASK … #define CS42L43_ASP_RX_CH5_EN_SHIFT … #define CS42L43_ASP_RX_CH4_EN_MASK … #define CS42L43_ASP_RX_CH4_EN_SHIFT … #define CS42L43_ASP_RX_CH3_EN_MASK … #define CS42L43_ASP_RX_CH3_EN_SHIFT … #define CS42L43_ASP_RX_CH2_EN_MASK … #define CS42L43_ASP_RX_CH2_EN_SHIFT … #define CS42L43_ASP_RX_CH1_EN_MASK … #define CS42L43_ASP_RX_CH1_EN_SHIFT … /* CS42L43_ASP_TX_EN */ #define CS42L43_ASP_TX_CH6_EN_MASK … #define CS42L43_ASP_TX_CH6_EN_SHIFT … #define CS42L43_ASP_TX_CH5_EN_MASK … #define CS42L43_ASP_TX_CH5_EN_SHIFT … #define CS42L43_ASP_TX_CH4_EN_MASK … #define CS42L43_ASP_TX_CH4_EN_SHIFT … #define CS42L43_ASP_TX_CH3_EN_MASK … #define CS42L43_ASP_TX_CH3_EN_SHIFT … #define CS42L43_ASP_TX_CH2_EN_MASK … #define CS42L43_ASP_TX_CH2_EN_SHIFT … #define CS42L43_ASP_TX_CH1_EN_MASK … #define CS42L43_ASP_TX_CH1_EN_SHIFT … /* CS42L43_ASP_RX_CH1_CTRL..CS42L43_ASP_TX_CH6_CTRL */ #define CS42L43_ASP_CH_WIDTH_MASK … #define CS42L43_ASP_CH_WIDTH_SHIFT … #define CS42L43_ASP_CH_SLOT_MASK … #define CS42L43_ASP_CH_SLOT_SHIFT … #define CS42L43_ASP_CH_SLOT_PHASE_MASK … #define CS42L43_ASP_CH_SLOT_PHASE_SHIFT … /* CS42L43_ASPTX1_INPUT..CS42L43_AMP4MIX_INPUT4 */ #define CS42L43_MIXER_VOL_MASK … #define CS42L43_MIXER_VOL_SHIFT … #define CS42L43_MIXER_SRC_MASK … #define CS42L43_MIXER_SRC_SHIFT … /* CS42L43_ASRC_INT_ENABLES */ #define CS42L43_ASRC_INT4_EN_MASK … #define CS42L43_ASRC_INT4_EN_SHIFT … #define CS42L43_ASRC_INT3_EN_MASK … #define CS42L43_ASRC_INT3_EN_SHIFT … #define CS42L43_ASRC_INT2_EN_MASK … #define CS42L43_ASRC_INT2_EN_SHIFT … #define CS42L43_ASRC_INT1_EN_MASK … #define CS42L43_ASRC_INT1_EN_SHIFT … /* CS42L43_ASRC_DEC_ENABLES */ #define CS42L43_ASRC_DEC4_EN_MASK … #define CS42L43_ASRC_DEC4_EN_SHIFT … #define CS42L43_ASRC_DEC3_EN_MASK … #define CS42L43_ASRC_DEC3_EN_SHIFT … #define CS42L43_ASRC_DEC2_EN_MASK … #define CS42L43_ASRC_DEC2_EN_SHIFT … #define CS42L43_ASRC_DEC1_EN_MASK … #define CS42L43_ASRC_DEC1_EN_SHIFT … /* CS42L43_PDNCNTL */ #define CS42L43_RING_SENSE_EN_MASK … #define CS42L43_RING_SENSE_EN_SHIFT … /* CS42L43_RINGSENSE_DEB_CTRL */ #define CS42L43_RINGSENSE_INV_MASK … #define CS42L43_RINGSENSE_INV_SHIFT … #define CS42L43_RINGSENSE_PULLUP_PDNB_MASK … #define CS42L43_RINGSENSE_PULLUP_PDNB_SHIFT … #define CS42L43_RINGSENSE_FALLING_DB_TIME_MASK … #define CS42L43_RINGSENSE_FALLING_DB_TIME_SHIFT … #define CS42L43_RINGSENSE_RISING_DB_TIME_MASK … #define CS42L43_RINGSENSE_RISING_DB_TIME_SHIFT … /* CS42L43_TIPSENSE_DEB_CTRL */ #define CS42L43_TIPSENSE_INV_MASK … #define CS42L43_TIPSENSE_INV_SHIFT … #define CS42L43_TIPSENSE_FALLING_DB_TIME_MASK … #define CS42L43_TIPSENSE_FALLING_DB_TIME_SHIFT … #define CS42L43_TIPSENSE_RISING_DB_TIME_MASK … #define CS42L43_TIPSENSE_RISING_DB_TIME_SHIFT … /* CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS */ #define CS42L43_TIPSENSE_UNPLUG_DB_STS_MASK … #define CS42L43_TIPSENSE_UNPLUG_DB_STS_SHIFT … #define CS42L43_TIPSENSE_PLUG_DB_STS_MASK … #define CS42L43_TIPSENSE_PLUG_DB_STS_SHIFT … #define CS42L43_RINGSENSE_UNPLUG_DB_STS_MASK … #define CS42L43_RINGSENSE_UNPLUG_DB_STS_SHIFT … #define CS42L43_RINGSENSE_PLUG_DB_STS_MASK … #define CS42L43_RINGSENSE_PLUG_DB_STS_SHIFT … /* CS42L43_HS2 */ #define CS42L43_HS_CLAMP_DISABLE_MASK … #define CS42L43_HS_CLAMP_DISABLE_SHIFT … #define CS42L43_HSBIAS_RAMP_MASK … #define CS42L43_HSBIAS_RAMP_SHIFT … #define CS42L43_HSDET_MODE_MASK … #define CS42L43_HSDET_MODE_SHIFT … #define CS42L43_HSDET_MANUAL_MODE_MASK … #define CS42L43_HSDET_MANUAL_MODE_SHIFT … #define CS42L43_AUTO_HSDET_TIME_MASK … #define CS42L43_AUTO_HSDET_TIME_SHIFT … #define CS42L43_AMP3_4_GNDREF_HS3_SEL_MASK … #define CS42L43_AMP3_4_GNDREF_HS3_SEL_SHIFT … #define CS42L43_AMP3_4_GNDREF_HS4_SEL_MASK … #define CS42L43_AMP3_4_GNDREF_HS4_SEL_SHIFT … #define CS42L43_HSBIAS_GNDREF_HS3_SEL_MASK … #define CS42L43_HSBIAS_GNDREF_HS3_SEL_SHIFT … #define CS42L43_HSBIAS_GNDREF_HS4_SEL_MASK … #define CS42L43_HSBIAS_GNDREF_HS4_SEL_SHIFT … #define CS42L43_HSBIAS_OUT_HS3_SEL_MASK … #define CS42L43_HSBIAS_OUT_HS3_SEL_SHIFT … #define CS42L43_HSBIAS_OUT_HS4_SEL_MASK … #define CS42L43_HSBIAS_OUT_HS4_SEL_SHIFT … #define CS42L43_HSGND_HS3_SEL_MASK … #define CS42L43_HSGND_HS3_SEL_SHIFT … #define CS42L43_HSGND_HS4_SEL_MASK … #define CS42L43_HSGND_HS4_SEL_SHIFT … /* CS42L43_HS_STAT */ #define CS42L43_HSDET_TYPE_STS_MASK … #define CS42L43_HSDET_TYPE_STS_SHIFT … /* CS42L43_MCU_SW_INTERRUPT */ #define CS42L43_CONTROL_IND_MASK … #define CS42L43_CONTROL_IND_SHIFT … #define CS42L43_CONFIGS_IND_MASK … #define CS42L43_CONFIGS_IND_SHIFT … #define CS42L43_PATCH_IND_MASK … #define CS42L43_PATCH_IND_SHIFT … /* CS42L43_STEREO_MIC_CTRL */ #define CS42L43_HS2_BIAS_SENSE_EN_MASK … #define CS42L43_HS2_BIAS_SENSE_EN_SHIFT … #define CS42L43_HS1_BIAS_SENSE_EN_MASK … #define CS42L43_HS1_BIAS_SENSE_EN_SHIFT … #define CS42L43_HS2_BIAS_EN_MASK … #define CS42L43_HS2_BIAS_EN_SHIFT … #define CS42L43_HS1_BIAS_EN_MASK … #define CS42L43_HS1_BIAS_EN_SHIFT … #define CS42L43_JACK_STEREO_CONFIG_MASK … #define CS42L43_JACK_STEREO_CONFIG_SHIFT … /* CS42L43_STEREO_MIC_CLAMP_CTRL */ #define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_VAL_MASK … #define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_VAL_SHIFT … #define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_MASK … #define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_SHIFT … /* CS42L43_BLOCK_EN2 */ #define CS42L43_SPI_MSTR_EN_MASK … #define CS42L43_SPI_MSTR_EN_SHIFT … /* CS42L43_BLOCK_EN3 */ #define CS42L43_PDM2_DIN_R_EN_MASK … #define CS42L43_PDM2_DIN_R_EN_SHIFT … #define CS42L43_PDM2_DIN_L_EN_MASK … #define CS42L43_PDM2_DIN_L_EN_SHIFT … #define CS42L43_PDM1_DIN_R_EN_MASK … #define CS42L43_PDM1_DIN_R_EN_SHIFT … #define CS42L43_PDM1_DIN_L_EN_MASK … #define CS42L43_PDM1_DIN_L_EN_SHIFT … #define CS42L43_ADC2_EN_MASK … #define CS42L43_ADC2_EN_SHIFT … #define CS42L43_ADC1_EN_MASK … #define CS42L43_ADC1_EN_SHIFT … /* CS42L43_BLOCK_EN4 */ #define CS42L43_ASRC_DEC_BANK_EN_MASK … #define CS42L43_ASRC_DEC_BANK_EN_SHIFT … #define CS42L43_ASRC_INT_BANK_EN_MASK … #define CS42L43_ASRC_INT_BANK_EN_SHIFT … /* CS42L43_BLOCK_EN5 */ #define CS42L43_ISRC2_BANK_EN_MASK … #define CS42L43_ISRC2_BANK_EN_SHIFT … #define CS42L43_ISRC1_BANK_EN_MASK … #define CS42L43_ISRC1_BANK_EN_SHIFT … /* CS42L43_BLOCK_EN6 */ #define CS42L43_MIXER_EN_MASK … #define CS42L43_MIXER_EN_SHIFT … /* CS42L43_BLOCK_EN7 */ #define CS42L43_EQ_EN_MASK … #define CS42L43_EQ_EN_SHIFT … /* CS42L43_BLOCK_EN8 */ #define CS42L43_HP_EN_MASK … #define CS42L43_HP_EN_SHIFT … /* CS42L43_BLOCK_EN9 */ #define CS42L43_TONE_EN_MASK … #define CS42L43_TONE_EN_SHIFT … /* CS42L43_BLOCK_EN10 */ #define CS42L43_AMP2_EN_MASK … #define CS42L43_AMP2_EN_SHIFT … #define CS42L43_AMP1_EN_MASK … #define CS42L43_AMP1_EN_SHIFT … /* CS42L43_BLOCK_EN11 */ #define CS42L43_SPDIF_EN_MASK … #define CS42L43_SPDIF_EN_SHIFT … /* CS42L43_TONE_CH1_CTRL..CS42L43_TONE_CH2_CTRL */ #define CS42L43_TONE_FREQ_MASK … #define CS42L43_TONE_FREQ_SHIFT … #define CS42L43_TONE_SEL_MASK … #define CS42L43_TONE_SEL_SHIFT … /* CS42L43_MIC_DETECT_CONTROL_1 */ #define CS42L43_BUTTON_DETECT_MODE_MASK … #define CS42L43_BUTTON_DETECT_MODE_SHIFT … #define CS42L43_HSBIAS_MODE_MASK … #define CS42L43_HSBIAS_MODE_SHIFT … #define CS42L43_MIC_LVL_DET_DISABLE_MASK … #define CS42L43_MIC_LVL_DET_DISABLE_SHIFT … /* CS42L43_DETECT_STATUS_1 */ #define CS42L43_HSDET_DC_STS_MASK … #define CS42L43_HSDET_DC_STS_SHIFT … #define CS42L43_JACKDET_STS_MASK … #define CS42L43_JACKDET_STS_SHIFT … #define CS42L43_HSBIAS_CLAMP_STS_MASK … #define CS42L43_HSBIAS_CLAMP_STS_SHIFT … /* CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL */ #define CS42L43_JACKDET_MODE_MASK … #define CS42L43_JACKDET_MODE_SHIFT … #define CS42L43_JACKDET_INV_MASK … #define CS42L43_JACKDET_INV_SHIFT … #define CS42L43_JACKDET_DB_TIME_MASK … #define CS42L43_JACKDET_DB_TIME_SHIFT … #define CS42L43_S0_AUTO_ADCMUTE_DISABLE_MASK … #define CS42L43_S0_AUTO_ADCMUTE_DISABLE_SHIFT … #define CS42L43_HSBIAS_SENSE_EN_MASK … #define CS42L43_HSBIAS_SENSE_EN_SHIFT … #define CS42L43_AUTO_HSBIAS_CLAMP_EN_MASK … #define CS42L43_AUTO_HSBIAS_CLAMP_EN_SHIFT … #define CS42L43_JACKDET_SENSE_EN_MASK … #define CS42L43_JACKDET_SENSE_EN_SHIFT … #define CS42L43_HSBIAS_SENSE_TRIP_MASK … #define CS42L43_HSBIAS_SENSE_TRIP_SHIFT … /* CS42L43_MIC_DETECT_CONTROL_ANDROID */ #define CS42L43_HSDET_LVL_COMBWIDTH_MASK … #define CS42L43_HSDET_LVL_COMBWIDTH_SHIFT … #define CS42L43_HSDET_LVL2_THRESH_MASK … #define CS42L43_HSDET_LVL2_THRESH_SHIFT … #define CS42L43_HSDET_LVL1_THRESH_MASK … #define CS42L43_HSDET_LVL1_THRESH_SHIFT … /* CS42L43_ISRC1_CTRL..CS42L43_ISRC2_CTRL */ #define CS42L43_ISRC_INT2_EN_MASK … #define CS42L43_ISRC_INT2_EN_SHIFT … #define CS42L43_ISRC_INT1_EN_MASK … #define CS42L43_ISRC_INT1_EN_SHIFT … #define CS42L43_ISRC_DEC2_EN_MASK … #define CS42L43_ISRC_DEC2_EN_SHIFT … #define CS42L43_ISRC_DEC1_EN_MASK … #define CS42L43_ISRC_DEC1_EN_SHIFT … /* CS42L43_CTRL_REG */ #define CS42L43_PLL_MODE_BYPASS_500_MASK … #define CS42L43_PLL_MODE_BYPASS_500_SHIFT … #define CS42L43_PLL_MODE_BYPASS_1029_MASK … #define CS42L43_PLL_MODE_BYPASS_1029_SHIFT … #define CS42L43_PLL_EN_MASK … #define CS42L43_PLL_EN_SHIFT … /* CS42L43_FDIV_FRAC */ #define CS42L43_PLL_DIV_INT_MASK … #define CS42L43_PLL_DIV_INT_SHIFT … #define CS42L43_PLL_DIV_FRAC_BYTE2_MASK … #define CS42L43_PLL_DIV_FRAC_BYTE2_SHIFT … #define CS42L43_PLL_DIV_FRAC_BYTE1_MASK … #define CS42L43_PLL_DIV_FRAC_BYTE1_SHIFT … #define CS42L43_PLL_DIV_FRAC_BYTE0_MASK … #define CS42L43_PLL_DIV_FRAC_BYTE0_SHIFT … /* CS42L43_CAL_RATIO */ #define CS42L43_PLL_CAL_RATIO_MASK … #define CS42L43_PLL_CAL_RATIO_SHIFT … /* CS42L43_SPI_CLK_CONFIG1 */ #define CS42L43_SCLK_DIV_MASK … #define CS42L43_SCLK_DIV_SHIFT … /* CS42L43_SPI_CONFIG1 */ #define CS42L43_SPI_SS_IDLE_DUR_MASK … #define CS42L43_SPI_SS_IDLE_DUR_SHIFT … #define CS42L43_SPI_SS_DELAY_DUR_MASK … #define CS42L43_SPI_SS_DELAY_DUR_SHIFT … #define CS42L43_SPI_THREE_WIRE_MASK … #define CS42L43_SPI_THREE_WIRE_SHIFT … #define CS42L43_SPI_DPHA_MASK … #define CS42L43_SPI_DPHA_SHIFT … #define CS42L43_SPI_CPHA_MASK … #define CS42L43_SPI_CPHA_SHIFT … #define CS42L43_SPI_CPOL_MASK … #define CS42L43_SPI_CPOL_SHIFT … #define CS42L43_SPI_SS_SEL_MASK … #define CS42L43_SPI_SS_SEL_SHIFT … /* CS42L43_SPI_CONFIG2 */ #define CS42L43_SPI_SS_FRC_MASK … #define CS42L43_SPI_SS_FRC_SHIFT … /* CS42L43_SPI_CONFIG3 */ #define CS42L43_SPI_WDT_ENA_MASK … #define CS42L43_SPI_WDT_ENA_SHIFT … /* CS42L43_SPI_CONFIG4 */ #define CS42L43_SPI_STALL_ENA_MASK … #define CS42L43_SPI_STALL_ENA_SHIFT … /* CS42L43_SPI_STATUS1 */ #define CS42L43_SPI_ABORT_STS_MASK … #define CS42L43_SPI_ABORT_STS_SHIFT … #define CS42L43_SPI_DONE_STS_MASK … #define CS42L43_SPI_DONE_STS_SHIFT … /* CS42L43_SPI_STATUS2 */ #define CS42L43_SPI_RX_DONE_STS_MASK … #define CS42L43_SPI_RX_DONE_STS_SHIFT … #define CS42L43_SPI_TX_DONE_STS_MASK … #define CS42L43_SPI_TX_DONE_STS_SHIFT … /* CS42L43_TRAN_CONFIG1 */ #define CS42L43_SPI_START_MASK … #define CS42L43_SPI_START_SHIFT … /* CS42L43_TRAN_CONFIG2 */ #define CS42L43_SPI_ABORT_MASK … #define CS42L43_SPI_ABORT_SHIFT … /* CS42L43_TRAN_CONFIG3 */ #define CS42L43_SPI_WORD_SIZE_MASK … #define CS42L43_SPI_WORD_SIZE_SHIFT … #define CS42L43_SPI_CMD_MASK … #define CS42L43_SPI_CMD_SHIFT … /* CS42L43_TRAN_CONFIG4 */ #define CS42L43_SPI_TX_LENGTH_MASK … #define CS42L43_SPI_TX_LENGTH_SHIFT … /* CS42L43_TRAN_CONFIG5 */ #define CS42L43_SPI_RX_LENGTH_MASK … #define CS42L43_SPI_RX_LENGTH_SHIFT … /* CS42L43_TRAN_CONFIG6 */ #define CS42L43_SPI_TX_BLOCK_LENGTH_MASK … #define CS42L43_SPI_TX_BLOCK_LENGTH_SHIFT … /* CS42L43_TRAN_CONFIG7 */ #define CS42L43_SPI_RX_BLOCK_LENGTH_MASK … #define CS42L43_SPI_RX_BLOCK_LENGTH_SHIFT … /* CS42L43_TRAN_CONFIG8 */ #define CS42L43_SPI_RX_DONE_MASK … #define CS42L43_SPI_RX_DONE_SHIFT … #define CS42L43_SPI_TX_DONE_MASK … #define CS42L43_SPI_TX_DONE_SHIFT … /* CS42L43_TRAN_STATUS1 */ #define CS42L43_SPI_BUSY_STS_MASK … #define CS42L43_SPI_BUSY_STS_SHIFT … #define CS42L43_SPI_RX_REQUEST_MASK … #define CS42L43_SPI_RX_REQUEST_SHIFT … #define CS42L43_SPI_TX_REQUEST_MASK … #define CS42L43_SPI_TX_REQUEST_SHIFT … /* CS42L43_TRAN_STATUS2 */ #define CS42L43_SPI_TX_BYTE_COUNT_MASK … #define CS42L43_SPI_TX_BYTE_COUNT_SHIFT … /* CS42L43_TRAN_STATUS3 */ #define CS42L43_SPI_RX_BYTE_COUNT_MASK … #define CS42L43_SPI_RX_BYTE_COUNT_SHIFT … /* CS42L43_TX_DATA */ #define CS42L43_SPI_TX_DATA_MASK … #define CS42L43_SPI_TX_DATA_SHIFT … /* CS42L43_RX_DATA */ #define CS42L43_SPI_RX_DATA_MASK … #define CS42L43_SPI_RX_DATA_SHIFT … /* CS42L43_DACCNFG1 */ #define CS42L43_HP_MSTR_VOL_CTRL_EN_MASK … #define CS42L43_HP_MSTR_VOL_CTRL_EN_SHIFT … #define CS42L43_AMP4_INV_MASK … #define CS42L43_AMP4_INV_SHIFT … #define CS42L43_AMP3_INV_MASK … #define CS42L43_AMP3_INV_SHIFT … /* CS42L43_DACCNFG2 */ #define CS42L43_HP_AUTO_CLAMP_DISABLE_MASK … #define CS42L43_HP_AUTO_CLAMP_DISABLE_SHIFT … #define CS42L43_HP_HPF_EN_MASK … #define CS42L43_HP_HPF_EN_SHIFT … /* CS42L43_HPPATHVOL */ #define CS42L43_AMP4_PATH_VOL_MASK … #define CS42L43_AMP4_PATH_VOL_SHIFT … #define CS42L43_AMP3_PATH_VOL_MASK … #define CS42L43_AMP3_PATH_VOL_SHIFT … /* CS42L43_PGAVOL */ #define CS42L43_HP_PATH_VOL_RAMP_MASK … #define CS42L43_HP_PATH_VOL_RAMP_SHIFT … #define CS42L43_HP_PATH_VOL_ZC_MASK … #define CS42L43_HP_PATH_VOL_ZC_SHIFT … #define CS42L43_HP_PATH_VOL_SFT_MASK … #define CS42L43_HP_PATH_VOL_SFT_SHIFT … #define CS42L43_HP_DIG_VOL_RAMP_MASK … #define CS42L43_HP_DIG_VOL_RAMP_SHIFT … #define CS42L43_HP_ANA_VOL_RAMP_MASK … #define CS42L43_HP_ANA_VOL_RAMP_SHIFT … /* CS42L43_LOADDETRESULTS */ #define CS42L43_AMP3_RES_DET_MASK … #define CS42L43_AMP3_RES_DET_SHIFT … /* CS42L43_LOADDETENA */ #define CS42L43_HPLOAD_DET_EN_MASK … #define CS42L43_HPLOAD_DET_EN_SHIFT … /* CS42L43_CTRL */ #define CS42L43_ADPTPWR_MODE_MASK … #define CS42L43_ADPTPWR_MODE_SHIFT … /* CS42L43_COEFF_RD_WR0 */ #define CS42L43_WRITE_MODE_MASK … #define CS42L43_WRITE_MODE_SHIFT … /* CS42L43_INIT_DONE0 */ #define CS42L43_INITIALIZE_DONE_MASK … #define CS42L43_INITIALIZE_DONE_SHIFT … /* CS42L43_START_EQZ0 */ #define CS42L43_START_FILTER_MASK … #define CS42L43_START_FILTER_SHIFT … /* CS42L43_MUTE_EQ_IN0 */ #define CS42L43_MUTE_EQ_CH2_MASK … #define CS42L43_MUTE_EQ_CH2_SHIFT … #define CS42L43_MUTE_EQ_CH1_MASK … #define CS42L43_MUTE_EQ_CH1_SHIFT … /* CS42L43_PLL_INT */ #define CS42L43_PLL_LOST_LOCK_INT_MASK … #define CS42L43_PLL_LOST_LOCK_INT_SHIFT … #define CS42L43_PLL_READY_INT_MASK … #define CS42L43_PLL_READY_INT_SHIFT … /* CS42L43_SOFT_INT */ #define CS42L43_CONTROL_APPLIED_INT_MASK … #define CS42L43_CONTROL_APPLIED_INT_SHIFT … #define CS42L43_CONTROL_WARN_INT_MASK … #define CS42L43_CONTROL_WARN_INT_SHIFT … #define CS42L43_PATCH_WARN_INT_MASK … #define CS42L43_PATCH_WARN_INT_SHIFT … #define CS42L43_PATCH_APPLIED_INT_MASK … #define CS42L43_PATCH_APPLIED_INT_SHIFT … /* CS42L43_MSM_INT */ #define CS42L43_HP_STARTUP_DONE_INT_MASK … #define CS42L43_HP_STARTUP_DONE_INT_SHIFT … #define CS42L43_HP_SHUTDOWN_DONE_INT_MASK … #define CS42L43_HP_SHUTDOWN_DONE_INT_SHIFT … #define CS42L43_HSDET_DONE_INT_MASK … #define CS42L43_HSDET_DONE_INT_SHIFT … #define CS42L43_TIPSENSE_UNPLUG_DB_INT_MASK … #define CS42L43_TIPSENSE_UNPLUG_DB_INT_SHIFT … #define CS42L43_TIPSENSE_PLUG_DB_INT_MASK … #define CS42L43_TIPSENSE_PLUG_DB_INT_SHIFT … #define CS42L43_RINGSENSE_UNPLUG_DB_INT_MASK … #define CS42L43_RINGSENSE_UNPLUG_DB_INT_SHIFT … #define CS42L43_RINGSENSE_PLUG_DB_INT_MASK … #define CS42L43_RINGSENSE_PLUG_DB_INT_SHIFT … #define CS42L43_TIPSENSE_UNPLUG_PDET_INT_MASK … #define CS42L43_TIPSENSE_UNPLUG_PDET_INT_SHIFT … #define CS42L43_TIPSENSE_PLUG_PDET_INT_MASK … #define CS42L43_TIPSENSE_PLUG_PDET_INT_SHIFT … #define CS42L43_RINGSENSE_UNPLUG_PDET_INT_MASK … #define CS42L43_RINGSENSE_UNPLUG_PDET_INT_SHIFT … #define CS42L43_RINGSENSE_PLUG_PDET_INT_MASK … #define CS42L43_RINGSENSE_PLUG_PDET_INT_SHIFT … /* CS42L43_ACC_DET_INT */ #define CS42L43_HS2_BIAS_SENSE_INT_MASK … #define CS42L43_HS2_BIAS_SENSE_INT_SHIFT … #define CS42L43_HS1_BIAS_SENSE_INT_MASK … #define CS42L43_HS1_BIAS_SENSE_INT_SHIFT … #define CS42L43_DC_DETECT1_FALSE_INT_MASK … #define CS42L43_DC_DETECT1_FALSE_INT_SHIFT … #define CS42L43_DC_DETECT1_TRUE_INT_MASK … #define CS42L43_DC_DETECT1_TRUE_INT_SHIFT … #define CS42L43_HSBIAS_CLAMPED_INT_MASK … #define CS42L43_HSBIAS_CLAMPED_INT_SHIFT … #define CS42L43_HS3_4_BIAS_SENSE_INT_MASK … #define CS42L43_HS3_4_BIAS_SENSE_INT_SHIFT … /* CS42L43_SPI_MSTR_INT */ #define CS42L43_IRQ_SPI_STALLING_INT_MASK … #define CS42L43_IRQ_SPI_STALLING_INT_SHIFT … #define CS42L43_IRQ_SPI_STS_INT_MASK … #define CS42L43_IRQ_SPI_STS_INT_SHIFT … #define CS42L43_IRQ_SPI_BLOCK_INT_MASK … #define CS42L43_IRQ_SPI_BLOCK_INT_SHIFT … /* CS42L43_SW_TO_SPI_BRIDGE_INT */ #define CS42L43_SW2SPI_BUF_OVF_UDF_INT_MASK … #define CS42L43_SW2SPI_BUF_OVF_UDF_INT_SHIFT … /* CS42L43_CLASS_D_AMP_INT */ #define CS42L43_AMP2_CLK_STOP_FAULT_INT_MASK … #define CS42L43_AMP2_CLK_STOP_FAULT_INT_SHIFT … #define CS42L43_AMP1_CLK_STOP_FAULT_INT_MASK … #define CS42L43_AMP1_CLK_STOP_FAULT_INT_SHIFT … #define CS42L43_AMP2_VDDSPK_FAULT_INT_MASK … #define CS42L43_AMP2_VDDSPK_FAULT_INT_SHIFT … #define CS42L43_AMP1_VDDSPK_FAULT_INT_MASK … #define CS42L43_AMP1_VDDSPK_FAULT_INT_SHIFT … #define CS42L43_AMP2_SHUTDOWN_DONE_INT_MASK … #define CS42L43_AMP2_SHUTDOWN_DONE_INT_SHIFT … #define CS42L43_AMP1_SHUTDOWN_DONE_INT_MASK … #define CS42L43_AMP1_SHUTDOWN_DONE_INT_SHIFT … #define CS42L43_AMP2_STARTUP_DONE_INT_MASK … #define CS42L43_AMP2_STARTUP_DONE_INT_SHIFT … #define CS42L43_AMP1_STARTUP_DONE_INT_MASK … #define CS42L43_AMP1_STARTUP_DONE_INT_SHIFT … #define CS42L43_AMP2_THERM_SHDN_INT_MASK … #define CS42L43_AMP2_THERM_SHDN_INT_SHIFT … #define CS42L43_AMP1_THERM_SHDN_INT_MASK … #define CS42L43_AMP1_THERM_SHDN_INT_SHIFT … #define CS42L43_AMP2_THERM_WARN_INT_MASK … #define CS42L43_AMP2_THERM_WARN_INT_SHIFT … #define CS42L43_AMP1_THERM_WARN_INT_MASK … #define CS42L43_AMP1_THERM_WARN_INT_SHIFT … #define CS42L43_AMP2_SCDET_INT_MASK … #define CS42L43_AMP2_SCDET_INT_SHIFT … #define CS42L43_AMP1_SCDET_INT_MASK … #define CS42L43_AMP1_SCDET_INT_SHIFT … /* CS42L43_GPIO_INT */ #define CS42L43_GPIO3_FALL_INT_MASK … #define CS42L43_GPIO3_FALL_INT_SHIFT … #define CS42L43_GPIO3_RISE_INT_MASK … #define CS42L43_GPIO3_RISE_INT_SHIFT … #define CS42L43_GPIO2_FALL_INT_MASK … #define CS42L43_GPIO2_FALL_INT_SHIFT … #define CS42L43_GPIO2_RISE_INT_MASK … #define CS42L43_GPIO2_RISE_INT_SHIFT … #define CS42L43_GPIO1_FALL_INT_MASK … #define CS42L43_GPIO1_FALL_INT_SHIFT … #define CS42L43_GPIO1_RISE_INT_MASK … #define CS42L43_GPIO1_RISE_INT_SHIFT … /* CS42L43_HPOUT_INT */ #define CS42L43_HP_ILIMIT_INT_MASK … #define CS42L43_HP_ILIMIT_INT_SHIFT … #define CS42L43_HP_LOADDET_DONE_INT_MASK … #define CS42L43_HP_LOADDET_DONE_INT_SHIFT … /* CS42L43_BOOT_CONTROL */ #define CS42L43_LOCK_HW_STS_MASK … #define CS42L43_LOCK_HW_STS_SHIFT … /* CS42L43_BLOCK_EN */ #define CS42L43_MCU_EN_MASK … #define CS42L43_MCU_EN_SHIFT … /* CS42L43_SHUTTER_CONTROL */ #define CS42L43_STATUS_SPK_SHUTTER_MUTE_MASK … #define CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT … #define CS42L43_SPK_SHUTTER_CFG_MASK … #define CS42L43_SPK_SHUTTER_CFG_SHIFT … #define CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK … #define CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT … #define CS42L43_MIC_SHUTTER_CFG_MASK … #define CS42L43_MIC_SHUTTER_CFG_SHIFT … /* CS42L43_MCU_SW_REV */ #define CS42L43_BIOS_SUBMINOR_REV_MASK … #define CS42L43_BIOS_SUBMINOR_REV_SHIFT … #define CS42L43_BIOS_MINOR_REV_MASK … #define CS42L43_BIOS_MINOR_REV_SHIFT … #define CS42L43_BIOS_MAJOR_REV_MASK … #define CS42L43_BIOS_MAJOR_REV_SHIFT … #define CS42L43_FW_SUBMINOR_REV_MASK … #define CS42L43_FW_SUBMINOR_REV_SHIFT … #define CS42L43_FW_MINOR_REV_MASK … #define CS42L43_FW_MINOR_REV_SHIFT … #define CS42L43_FW_MAJOR_REV_MASK … #define CS42L43_FW_MAJOR_REV_SHIFT … /* CS42L43_NEED_CONFIGS */ #define CS42L43_FW_PATCH_NEED_CFG_MASK … #define CS42L43_FW_PATCH_NEED_CFG_SHIFT … /* CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION */ #define CS42L43_FW_MM_CTRL_MCU_SEL_MASK … #define CS42L43_FW_MM_CTRL_MCU_SEL_SHIFT … /* CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG */ #define CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL … #endif /* CS42L43_CORE_REGS_H */
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