/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2014 MediaTek Inc. * Author: Hongzhou.Yang <[email protected]> */ #ifndef __PINCTRL_MTK_COMMON_H #define __PINCTRL_MTK_COMMON_H #include <linux/pinctrl/pinctrl.h> #include <linux/regmap.h> #include <linux/pinctrl/pinconf-generic.h> #include "mtk-eint.h" #define NO_EINT_SUPPORT … #define MT_EDGE_SENSITIVE … #define MT_LEVEL_SENSITIVE … #define EINT_DBNC_SET_DBNC_BITS … #define EINT_DBNC_RST_BIT … #define EINT_DBNC_SET_EN … #define MTK_PINCTRL_NOT_SUPPORT … struct mtk_desc_function { … }; struct mtk_desc_eint { … }; struct mtk_desc_pin { … }; #define MTK_PIN(_pin, _pad, _chip, _eint, ...) … #define MTK_EINT_FUNCTION(_eintmux, _eintnum) … #define MTK_FUNCTION(_val, _name) … #define SET_ADDR(x, y) … #define CLR_ADDR(x, y) … struct mtk_pinctrl_group { … }; /** * struct mtk_drv_group_desc - Provide driving group data. * @max_drv: The maximum current of this group. * @min_drv: The minimum current of this group. * @low_bit: The lowest bit of this group. * @high_bit: The highest bit of this group. * @step: The step current of this group. */ struct mtk_drv_group_desc { … }; #define MTK_DRV_GRP(_min, _max, _low, _high, _step) … /** * struct mtk_pin_drv_grp - Provide each pin driving info. * @pin: The pin number. * @offset: The offset of driving register for this pin. * @bit: The bit of driving register for this pin. * @grp: The group for this pin belongs to. */ struct mtk_pin_drv_grp { … }; #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) … /** * struct mtk_pin_spec_pupd_set_samereg * - For special pins' pull up/down setting which resides in same register * @pin: The pin number. * @offset: The offset of special pull up/down setting register. * @pupd_bit: The pull up/down bit in this register. * @r0_bit: The r0 bit of pull resistor. * @r1_bit: The r1 bit of pull resistor. */ struct mtk_pin_spec_pupd_set_samereg { … }; #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) … /** * struct mtk_pin_ies_set - For special pins' ies and smt setting. * @start: The start pin number of those special pins. * @end: The end pin number of those special pins. * @offset: The offset of special setting register. * @bit: The bit of special setting register. */ struct mtk_pin_ies_smt_set { … }; #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) … struct mtk_eint_offsets { … }; /** * struct mtk_pinctrl_devdata - Provide HW GPIO related data. * @pins: An array describing all pins the pin controller affects. * @npins: The number of entries in @pins. * * @grp_desc: The driving group info. * @pin_drv_grp: The driving group for all pins. * @spec_ies: Special pin setting for input enable * @n_spec_ies: Number of entries in spec_ies * @spec_pupd: Special pull up/down setting * @n_spec_pupd: Number of entries in spec_pupd * @spec_smt: Special pin setting for schmitt * @n_spec_smt: Number of entries in spec_smt * @spec_pull_set: Each SoC may have special pins for pull up/down setting, * these pins' pull setting are very different, they have separate pull * up/down bit, R0 and R1 resistor bit, so they need special pull setting. * If special setting is success, this should return 0, otherwise it should * return non-zero value. * @spec_ies_smt_set: Some pins are irregular, their input enable and smt * control register are discontinuous, but they are mapping together. That * means when user set smt, input enable is set at the same time. So they * also need special control. If special control is success, this should * return 0, otherwise return non-zero value. * @spec_pinmux_set: In some cases, there are two pinmux functions share * the same value in the same segment of pinmux control register. If user * want to use one of the two functions, they need an extra bit setting to * select the right one. * @spec_dir_set: In very few SoCs, direction control registers are not * arranged continuously, they may be cut to parts. So they need special * dir setting. * @mt8365_set_clr_mode: In mt8365, some pins won't set correcty because they * need to use the main R/W register to read/update/write the modes instead of * the SET/CLR register. * * @dir_offset: The direction register offset. * @pullen_offset: The pull-up/pull-down enable register offset. * @pinmux_offset: The pinmux register offset. * * @type1_start: Some chips have two base addresses for pull select register, * that means some pins use the first address and others use the second. This * member record the start of pin number to use the second address. * @type1_end: The end of pin number to use the second address. * * @port_shf: The shift between two registers. * @port_mask: The mask of register. * @port_align: Provide clear register and set register step. */ struct mtk_pinctrl_devdata { … }; struct mtk_pinctrl { … }; int mtk_pctrl_init(struct platform_device *pdev, const struct mtk_pinctrl_devdata *data, struct regmap *regmap); int mtk_pctrl_common_probe(struct platform_device *pdev); int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, const struct mtk_pinctrl_devdata *devdata, unsigned int pin, bool isup, unsigned int r1r0); int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, const struct mtk_pinctrl_devdata *devdata, unsigned int pin, int value, enum pin_config_param arg); extern const struct dev_pm_ops mtk_eint_pm_ops; #endif /* __PINCTRL_MTK_COMMON_H */
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