linux/drivers/gpu/drm/xe/xe_hw_fence_types.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2022 Intel Corporation
 */

#ifndef _XE_HW_FENCE_TYPES_H_
#define _XE_HW_FENCE_TYPES_H_

#include <linux/dma-fence.h>
#include <linux/iosys-map.h>
#include <linux/irq_work.h>
#include <linux/list.h>
#include <linux/spinlock.h>

struct xe_gt;

/**
 * struct xe_hw_fence_irq - hardware fence IRQ handler
 *
 * One per engine class, signals completed xe_hw_fences, triggered via hw engine
 * interrupt. On each trigger, search list of pending fences and signal.
 */
struct xe_hw_fence_irq { … };

#define MAX_FENCE_NAME_LEN …

/**
 * struct xe_hw_fence_ctx - hardware fence context
 *
 * The context for a hardware fence. 1 to 1 relationship with xe_engine. Points
 * to a xe_hw_fence_irq, maintains serial seqno.
 */
struct xe_hw_fence_ctx { … };

/**
 * struct xe_hw_fence - hardware fence
 *
 * Used to indicate a xe_sched_job is complete via a seqno written to memory.
 * Signals on error or seqno past.
 */
struct xe_hw_fence { … };

#endif