/* SPDX-License-Identifier: MIT */ /* * Copyright © 2022-2023 Intel Corporation */ #ifndef _XE_GT_TYPES_H_ #define _XE_GT_TYPES_H_ #include "xe_force_wake_types.h" #include "xe_gt_idle_types.h" #include "xe_gt_sriov_pf_types.h" #include "xe_gt_sriov_vf_types.h" #include "xe_hw_engine_types.h" #include "xe_hw_fence_types.h" #include "xe_oa.h" #include "xe_reg_sr_types.h" #include "xe_sa_types.h" #include "xe_uc_types.h" struct xe_exec_queue_ops; struct xe_migrate; struct xe_ring_ops; enum xe_gt_type { … }; #define XE_MAX_DSS_FUSE_REGS … #define XE_MAX_DSS_FUSE_BITS … #define XE_MAX_EU_FUSE_REGS … #define XE_MAX_EU_FUSE_BITS … #define XE_MAX_L3_BANK_MASK_BITS … xe_dss_mask_t; xe_eu_mask_t; xe_l3_bank_mask_t; struct xe_mmio_range { … }; /* * The hardware has multiple kinds of multicast register ranges that need * special register steering (and future platforms are expected to add * additional types). * * During driver startup, we initialize the steering control register to * direct reads to a slice/subslice that are valid for the 'subslice' class * of multicast registers. If another type of steering does not have any * overlap in valid steering targets with 'subslice' style registers, we will * need to explicitly re-steer reads of registers of the other type. * * Only the replication types that may need additional non-default steering * are listed here. */ enum xe_steering_type { … }; #define gt_to_tile(gt__) … #define gt_to_xe(gt__) … /** * struct xe_gt - A "Graphics Technology" unit of the GPU * * A GT ("Graphics Technology") is the subset of a GPU primarily responsible * for implementing the graphics, compute, and/or media IP. It encapsulates * the hardware engines, programmable execution units, and GuC. Each GT has * its own handling of power management (RC6+forcewake) and multicast register * steering. * * A GPU/tile may have a single GT that supplies all graphics, compute, and * media functionality, or the graphics/compute and media may be split into * separate GTs within a tile. */ struct xe_gt { … }; #endif