/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef _XE_ENGINE_REGS_H_ #define _XE_ENGINE_REGS_H_ #include <asm/page.h> #include "regs/xe_reg_defs.h" /* * These *_BASE values represent the MMIO offset where each hardware engine's * registers start. The other definitions in this header are parameterized * macros that will take one of these values as a parameter. */ #define RENDER_RING_BASE … #define BSD_RING_BASE … #define BSD2_RING_BASE … #define BSD3_RING_BASE … #define BSD4_RING_BASE … #define XEHP_BSD5_RING_BASE … #define XEHP_BSD6_RING_BASE … #define XEHP_BSD7_RING_BASE … #define XEHP_BSD8_RING_BASE … #define VEBOX_RING_BASE … #define VEBOX2_RING_BASE … #define XEHP_VEBOX3_RING_BASE … #define XEHP_VEBOX4_RING_BASE … #define COMPUTE0_RING_BASE … #define COMPUTE1_RING_BASE … #define COMPUTE2_RING_BASE … #define COMPUTE3_RING_BASE … #define BLT_RING_BASE … #define XEHPC_BCS1_RING_BASE … #define XEHPC_BCS2_RING_BASE … #define XEHPC_BCS3_RING_BASE … #define XEHPC_BCS4_RING_BASE … #define XEHPC_BCS5_RING_BASE … #define XEHPC_BCS6_RING_BASE … #define XEHPC_BCS7_RING_BASE … #define XEHPC_BCS8_RING_BASE … #define GSCCS_RING_BASE … #define RING_TAIL(base) … #define TAIL_ADDR … #define RING_HEAD(base) … #define HEAD_ADDR … #define RING_START(base) … #define RING_CTL(base) … #define RING_CTL_SIZE(size) … #define RING_CTL_SIZE(size) … #define RING_START_UDW(base) … #define RING_PSMI_CTL(base) … #define RC_SEMA_IDLE_MSG_DISABLE … #define WAIT_FOR_EVENT_POWER_DOWN_DISABLE … #define IDLE_MSG_DISABLE … #define RING_PWRCTX_MAXCNT(base) … #define IDLE_WAIT_TIME … #define RING_ACTHD_UDW(base) … #define RING_DMA_FADD_UDW(base) … #define RING_IPEHR(base) … #define RING_INSTDONE(base) … #define RING_ACTHD(base) … #define RING_DMA_FADD(base) … #define RING_HWS_PGA(base) … #define RING_HWSTAM(base) … #define RING_MI_MODE(base) … #define RING_NOPID(base) … #define FF_THREAD_MODE(base) … #define FF_TESSELATION_DOP_GATE_DISABLE … #define RING_INT_SRC_RPT_PTR(base) … #define RING_IMR(base) … #define RING_INT_STATUS_RPT_PTR(base) … #define RING_EIR(base) … #define RING_EMR(base) … #define RING_ESR(base) … #define INSTPM(base) … #define ENABLE_SEMAPHORE_POLL_BIT … #define RING_CMD_CCTL(base) … /* * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. * The lsb of each can be considered a separate enabling bit for encryption. * 6:0 == default MOCS value for reads => 6:1 == table index for reads. * 13:7 == default MOCS value for writes => 13:8 == table index for writes. * 15:14 == Reserved => 31:30 are set to 0. */ #define CMD_CCTL_WRITE_OVERRIDE_MASK … #define CMD_CCTL_READ_OVERRIDE_MASK … #define CSFE_CHICKEN1(base) … #define GHWSP_CSB_REPORT_DIS … #define PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS … #define FF_SLICE_CS_CHICKEN1(base) … #define FFSC_PERCTX_PREEMPT_CTRL … #define CS_DEBUG_MODE1(base) … #define FF_DOP_CLOCK_GATE_DISABLE … #define REPLAY_MODE_GRANULARITY … #define INDIRECT_RING_STATE(base) … #define RING_BBADDR(base) … #define RING_BBADDR_UDW(base) … #define BCS_SWCTRL(base) … #define BCS_SWCTRL_DISABLE_256B … /* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */ #define BLIT_CCTL(base) … #define BLIT_CCTL_DST_MOCS_MASK … #define BLIT_CCTL_SRC_MOCS_MASK … #define RING_EXECLIST_STATUS_LO(base) … #define RING_EXECLIST_STATUS_HI(base) … #define RING_CONTEXT_CONTROL(base) … #define CTX_CTRL_OAC_CONTEXT_ENABLE … #define CTX_CTRL_RUN_ALONE … #define CTX_CTRL_INDIRECT_RING_STATE_ENABLE … #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH … #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT … #define RING_MODE(base) … #define GFX_DISABLE_LEGACY_MODE … #define RING_TIMESTAMP(base) … #define RING_TIMESTAMP_UDW(base) … #define RING_VALID_MASK … #define RING_VALID … #define STOP_RING … #define RING_CTX_TIMESTAMP(base) … #define CSBE_DEBUG_STATUS(base) … #define RING_FORCE_TO_NONPRIV(base, i) … #define RING_FORCE_TO_NONPRIV_DENY … #define RING_FORCE_TO_NONPRIV_ACCESS_MASK … #define RING_FORCE_TO_NONPRIV_ACCESS_RW … #define RING_FORCE_TO_NONPRIV_ACCESS_RD … #define RING_FORCE_TO_NONPRIV_ACCESS_WR … #define RING_FORCE_TO_NONPRIV_ACCESS_INVALID … #define RING_FORCE_TO_NONPRIV_ADDRESS_MASK … #define RING_FORCE_TO_NONPRIV_RANGE_MASK … #define RING_FORCE_TO_NONPRIV_RANGE_1 … #define RING_FORCE_TO_NONPRIV_RANGE_4 … #define RING_FORCE_TO_NONPRIV_RANGE_16 … #define RING_FORCE_TO_NONPRIV_RANGE_64 … #define RING_FORCE_TO_NONPRIV_MASK_VALID … #define RING_MAX_NONPRIV_SLOTS … #define RING_EXECLIST_SQ_CONTENTS_LO(base) … #define RING_EXECLIST_SQ_CONTENTS_HI(base) … #define RING_EXECLIST_CONTROL(base) … #define EL_CTRL_LOAD … #define CS_CHICKEN1(base) … #define PREEMPT_GPGPU_LEVEL(hi, lo) … #define PREEMPT_GPGPU_MID_THREAD_LEVEL … #define PREEMPT_GPGPU_THREAD_GROUP_LEVEL … #define PREEMPT_GPGPU_COMMAND_LEVEL … #define PREEMPT_GPGPU_LEVEL_MASK … #define PREEMPT_3D_OBJECT_LEVEL … #define VDBOX_CGCTL3F08(base) … #define CG3DDISHRS_CLKGATE_DIS … #define VDBOX_CGCTL3F10(base) … #define IECPUNIT_CLKGATE_DIS … #define VDBOX_CGCTL3F18(base) … #define ALNUNIT_CLKGATE_DIS … #define VDBOX_CGCTL3F1C(base) … #define MFXPIPE_CLKGATE_DIS … #endif
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