// SPDX-License-Identifier: MIT /* * Copyright © 2022 Intel Corporation */ #include "xe_guc.h" #include <drm/drm_managed.h> #include <generated/xe_wa_oob.h> #include "abi/guc_actions_abi.h" #include "abi/guc_errors_abi.h" #include "regs/xe_gt_regs.h" #include "regs/xe_gtt_defs.h" #include "regs/xe_guc_regs.h" #include "xe_bo.h" #include "xe_device.h" #include "xe_force_wake.h" #include "xe_gt.h" #include "xe_gt_printk.h" #include "xe_gt_sriov_vf.h" #include "xe_gt_throttle.h" #include "xe_guc_ads.h" #include "xe_guc_ct.h" #include "xe_guc_db_mgr.h" #include "xe_guc_hwconfig.h" #include "xe_guc_log.h" #include "xe_guc_pc.h" #include "xe_guc_relay.h" #include "xe_guc_submit.h" #include "xe_memirq.h" #include "xe_mmio.h" #include "xe_platform_types.h" #include "xe_sriov.h" #include "xe_uc.h" #include "xe_uc_fw.h" #include "xe_wa.h" #include "xe_wopcm.h" static u32 guc_bo_ggtt_addr(struct xe_guc *guc, struct xe_bo *bo) { … } static u32 guc_ctl_debug_flags(struct xe_guc *guc) { … } static u32 guc_ctl_feature_flags(struct xe_guc *guc) { … } static u32 guc_ctl_log_params_flags(struct xe_guc *guc) { … } static u32 guc_ctl_ads_flags(struct xe_guc *guc) { … } static u32 guc_ctl_wa_flags(struct xe_guc *guc) { … } static u32 guc_ctl_devid(struct xe_guc *guc) { … } static void guc_print_params(struct xe_guc *guc) { … } static void guc_init_params(struct xe_guc *guc) { … } static void guc_init_params_post_hwconfig(struct xe_guc *guc) { … } /* * Initialize the GuC parameter block before starting the firmware * transfer. These parameters are read by the firmware on startup * and cannot be changed thereafter. */ static void guc_write_params(struct xe_guc *guc) { … } static void guc_fini_hw(void *arg) { … } /** * xe_guc_comm_init_early - early initialization of GuC communication * @guc: the &xe_guc to initialize * * Must be called prior to first MMIO communication with GuC firmware. */ void xe_guc_comm_init_early(struct xe_guc *guc) { … } static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc) { … } static int vf_guc_init(struct xe_guc *guc) { … } int xe_guc_init(struct xe_guc *guc) { … } static int vf_guc_init_post_hwconfig(struct xe_guc *guc) { … } /** * xe_guc_init_post_hwconfig - initialize GuC post hwconfig load * @guc: The GuC object * * Return: 0 on success, negative error code on error. */ int xe_guc_init_post_hwconfig(struct xe_guc *guc) { … } int xe_guc_post_load_init(struct xe_guc *guc) { … } int xe_guc_reset(struct xe_guc *guc) { … } static void guc_prepare_xfer(struct xe_guc *guc) { … } /* * Supporting MMIO & in memory RSA */ static int guc_xfer_rsa(struct xe_guc *guc) { … } /* * Check a previously read GuC status register (GUC_STATUS) looking for * known terminal states (either completion or failure) of either the * microkernel status field or the boot ROM status field. Returns +1 for * successful completion, -1 for failure and 0 for any intermediate state. */ static int guc_load_done(u32 status) { … } static s32 guc_pc_get_cur_freq(struct xe_guc_pc *guc_pc) { … } /* * Wait for the GuC to start up. * * Measurements indicate this should take no more than 20ms (assuming the GT * clock is at maximum frequency). However, thermal throttling and other issues * can prevent the clock hitting max and thus making the load take significantly * longer. Allow up to 200ms as a safety margin for real world worst case situations. * * However, bugs anywhere from KMD to GuC to PCODE to fan failure in a CI farm can * lead to even longer times. E.g. if the GT is clamped to minimum frequency then * the load times can be in the seconds range. So the timeout is increased for debug * builds to ensure that problems can be correctly analysed. For release builds, the * timeout is kept short so that users don't wait forever to find out that there is a * problem. In either case, if the load took longer than is reasonable even with some * 'sensible' throttling, then flag a warning because something is not right. * * Note that there is a limit on how long an individual usleep_range() can wait for, * hence longer waits require wrapping a shorter wait in a loop. * * Note that the only reason an end user should hit the shorter timeout is in case of * extreme thermal throttling. And a system that is that hot during boot is probably * dead anyway! */ #if defined(CONFIG_DRM_XE_DEBUG) #define GUC_LOAD_RETRY_LIMIT … #else #define GUC_LOAD_RETRY_LIMIT … #endif #define GUC_LOAD_TIME_WARN_MS … static void guc_wait_ucode(struct xe_guc *guc) { … } static int __xe_guc_upload(struct xe_guc *guc) { … } static int vf_guc_min_load_for_hwconfig(struct xe_guc *guc) { … } /** * xe_guc_min_load_for_hwconfig - load minimal GuC and read hwconfig table * @guc: The GuC object * * This function uploads a minimal GuC that does not support submissions but * in a state where the hwconfig table can be read. Next, it reads and parses * the hwconfig table so it can be used for subsequent steps in the driver load. * Lastly, it enables CT communication (XXX: this is needed for PFs/VFs only). * * Return: 0 on success, negative error code on error. */ int xe_guc_min_load_for_hwconfig(struct xe_guc *guc) { … } int xe_guc_upload(struct xe_guc *guc) { … } static void guc_handle_mmio_msg(struct xe_guc *guc) { … } static void guc_enable_irq(struct xe_guc *guc) { … } int xe_guc_enable_communication(struct xe_guc *guc) { … } int xe_guc_suspend(struct xe_guc *guc) { … } void xe_guc_notify(struct xe_guc *guc) { … } int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) { … } int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, u32 len, u32 *response_buf) { … } int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len) { … } static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val) { … } int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val) { … } int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val) { … } void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir) { … } void xe_guc_sanitize(struct xe_guc *guc) { … } int xe_guc_reset_prepare(struct xe_guc *guc) { … } void xe_guc_reset_wait(struct xe_guc *guc) { … } void xe_guc_stop_prepare(struct xe_guc *guc) { … } void xe_guc_stop(struct xe_guc *guc) { … } int xe_guc_start(struct xe_guc *guc) { … } void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p) { … } /** * xe_guc_declare_wedged() - Declare GuC wedged * @guc: the GuC object * * Wedge the GuC which stops all submission, saves desired debug state, and * cleans up anything which could timeout. */ void xe_guc_declare_wedged(struct xe_guc *guc) { … }
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