linux/drivers/gpu/drm/xe/xe_heci_gsc.c

// SPDX-License-Identifier: MIT
/*
 * Copyright(c) 2023, Intel Corporation. All rights reserved.
 */

#include <linux/irq.h>
#include <linux/mei_aux.h>
#include <linux/pci.h>
#include <linux/sizes.h>

#include "xe_device_types.h"
#include "xe_drv.h"
#include "xe_heci_gsc.h"
#include "xe_platform_types.h"

#define GSC_BAR_LENGTH …

#define DG1_GSC_HECI2_BASE …
#define PVC_GSC_HECI2_BASE …
#define DG2_GSC_HECI2_BASE …

static void heci_gsc_irq_mask(struct irq_data *d)
{ … }

static void heci_gsc_irq_unmask(struct irq_data *d)
{ … }

static const struct irq_chip heci_gsc_irq_chip = …;

static int heci_gsc_irq_init(int irq)
{ … }

/**
 * struct heci_gsc_def - graphics security controller heci interface definitions
 *
 * @name: name of the heci device
 * @bar: address of the mmio bar
 * @bar_size: size of the mmio bar
 * @use_polling: indication of using polling mode for the device
 * @slow_firmware: indication of whether the device is slow (needs longer timeouts)
 */
struct heci_gsc_def { … };

/* gsc resources and definitions */
static const struct heci_gsc_def heci_gsc_def_dg1 = …;

static const struct heci_gsc_def heci_gsc_def_dg2 = …;

static const struct heci_gsc_def heci_gsc_def_pvc = …;

static void heci_gsc_release_dev(struct device *dev)
{ … }

void xe_heci_gsc_fini(struct xe_device *xe)
{ … }

static int heci_gsc_irq_setup(struct xe_device *xe)
{ … }

static int heci_gsc_add_device(struct xe_device *xe, const struct heci_gsc_def *def)
{ … }

void xe_heci_gsc_init(struct xe_device *xe)
{ … }

void xe_heci_gsc_irq_handler(struct xe_device *xe, u32 iir)
{ … }