linux/drivers/gpu/drm/xe/xe_irq.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2021 Intel Corporation
 */

#include "xe_irq.h"

#include <linux/sched/clock.h>

#include <drm/drm_managed.h>

#include "display/xe_display.h"
#include "regs/xe_gt_regs.h"
#include "regs/xe_regs.h"
#include "xe_device.h"
#include "xe_drv.h"
#include "xe_gsc_proxy.h"
#include "xe_gt.h"
#include "xe_guc.h"
#include "xe_hw_engine.h"
#include "xe_memirq.h"
#include "xe_mmio.h"
#include "xe_sriov.h"

/*
 * Interrupt registers for a unit are always consecutive and ordered
 * ISR, IMR, IIR, IER.
 */
#define IMR(offset) …
#define IIR(offset) …
#define IER(offset) …

static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
{ … }

/*
 * Unmask and enable the specified interrupts.  Does not check current state,
 * so any bits not specified here will become masked and disabled.
 */
static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits)
{ … }

/* Mask and disable all interrupts. */
static void mask_and_disable(struct xe_tile *tile, u32 irqregs)
{ … }

static u32 xelp_intr_disable(struct xe_device *xe)
{ … }

static u32
gu_misc_irq_ack(struct xe_device *xe, const u32 master_ctl)
{ … }

static inline void xelp_intr_enable(struct xe_device *xe, bool stall)
{ … }

/* Enable/unmask the HWE interrupts for a specific GT's engines. */
void xe_irq_enable_hwe(struct xe_gt *gt)
{ … }

static u32
gt_engine_identity(struct xe_device *xe,
		   struct xe_gt *mmio,
		   const unsigned int bank,
		   const unsigned int bit)
{ … }

#define OTHER_MEDIA_GUC_INSTANCE …

static void
gt_other_irq_handler(struct xe_gt *gt, const u8 instance, const u16 iir)
{ … }

static struct xe_gt *pick_engine_gt(struct xe_tile *tile,
				    enum xe_engine_class class,
				    unsigned int instance)
{ … }

static void gt_irq_handler(struct xe_tile *tile,
			   u32 master_ctl, unsigned long *intr_dw,
			   u32 *identity)
{ … }

/*
 * Top-level interrupt handler for Xe_LP platforms (which did not have
 * a "master tile" interrupt register.
 */
static irqreturn_t xelp_irq_handler(int irq, void *arg)
{ … }

static u32 dg1_intr_disable(struct xe_device *xe)
{ … }

static void dg1_intr_enable(struct xe_device *xe, bool stall)
{ … }

/*
 * Top-level interrupt handler for Xe_LP+ and beyond.  These platforms have
 * a "master tile" interrupt register which must be consulted before the
 * "graphics master" interrupt register.
 */
static irqreturn_t dg1_irq_handler(int irq, void *arg)
{ … }

static void gt_irq_reset(struct xe_tile *tile)
{ … }

static void xelp_irq_reset(struct xe_tile *tile)
{ … }

static void dg1_irq_reset(struct xe_tile *tile)
{ … }

static void dg1_irq_reset_mstr(struct xe_tile *tile)
{ … }

static void vf_irq_reset(struct xe_device *xe)
{ … }

static void xe_irq_reset(struct xe_device *xe)
{ … }

static void vf_irq_postinstall(struct xe_device *xe)
{ … }

static void xe_irq_postinstall(struct xe_device *xe)
{ … }

static irqreturn_t vf_mem_irq_handler(int irq, void *arg)
{ … }

static irq_handler_t xe_irq_handler(struct xe_device *xe)
{ … }

static void irq_uninstall(void *arg)
{ … }

int xe_irq_install(struct xe_device *xe)
{ … }

void xe_irq_suspend(struct xe_device *xe)
{ … }

void xe_irq_resume(struct xe_device *xe)
{ … }