// SPDX-License-Identifier: MIT /* * Copyright © 2022 Intel Corporation */ #include "xe_mocs.h" #include "regs/xe_gt_regs.h" #include "xe_bo.h" #include "xe_device.h" #include "xe_exec_queue.h" #include "xe_force_wake.h" #include "xe_gt.h" #include "xe_gt_mcr.h" #include "xe_gt_printk.h" #include "xe_mmio.h" #include "xe_platform_types.h" #include "xe_pm.h" #include "xe_sriov.h" #include "xe_step_types.h" #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) #define mocs_dbg … #else __printf(2, 3) static inline void mocs_dbg(const struct xe_gt *gt, const char *format, ...) { … } #endif enum { … }; struct xe_mocs_entry { … }; struct xe_mocs_info; struct xe_mocs_ops { … }; struct xe_mocs_info { … }; /* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */ #define IG_PAT … #define L3_CACHE_POLICY_MASK … #define L4_CACHE_POLICY_MASK … /* Helper defines */ #define XELP_NUM_MOCS_ENTRIES … #define PVC_NUM_MOCS_ENTRIES … #define MTL_NUM_MOCS_ENTRIES … #define XE2_NUM_MOCS_ENTRIES … /* (e)LLC caching options */ /* * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means * the same as LE_UC */ #define LE_0_PAGETABLE … #define LE_1_UC … #define LE_2_WT … #define LE_3_WB … /* Target cache */ #define LE_TC_0_PAGETABLE … #define LE_TC_1_LLC … #define LE_TC_2_LLC_ELLC … #define LE_TC_3_LLC_ELLC_ALT … /* L3 caching options */ #define L3_0_DIRECT … #define L3_1_UC … #define L3_2_RESERVED … #define L3_3_WB … /* L4 caching options */ #define L4_0_WB … #define L4_1_WT … #define L4_3_UC … #define XE2_L3_0_WB … /* XD: WB Transient Display */ #define XE2_L3_1_XD … #define XE2_L3_3_UC … #define XE2_L3_CLOS_MASK … #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) … /* * MOCS tables * * These are the MOCS tables that are programmed across all the rings. * The control value is programmed to all the rings that support the * MOCS registers. While the l3cc_values are only programmed to the * LNCFCMOCS0 - LNCFCMOCS32 registers. * * These tables are intended to be kept reasonably consistent across * HW platforms, and for ICL+, be identical across OSes. To achieve * that, the list of entries is published as part of bspec. * * Entries not part of the following tables are undefined as far as userspace is * concerned and shouldn't be relied upon. The last few entries are reserved by * the hardware. They should be initialized according to bspec and never used. * * NOTE1: These tables are part of bspec and defined as part of the hardware * interface. It is expected that, for specific hardware platform, existing * entries will remain constant and the table will only be updated by adding new * entries, filling unused positions. * * NOTE2: Reserved and unspecified MOCS indices have been set to L3 WB. These * reserved entries should never be used. They may be changed to low performant * variants with better coherency in the future if more entries are needed. */ static const struct xe_mocs_entry gen12_mocs_desc[] = …; static bool regs_are_mcr(struct xe_gt *gt) { … } static void xelp_lncf_dump(struct xe_mocs_info *info, struct xe_gt *gt, struct drm_printer *p) { … } static void xelp_mocs_dump(struct xe_mocs_info *info, unsigned int flags, struct xe_gt *gt, struct drm_printer *p) { … } static const struct xe_mocs_ops xelp_mocs_ops = …; static const struct xe_mocs_entry dg1_mocs_desc[] = …; static const struct xe_mocs_entry dg2_mocs_desc[] = …; static void xehp_lncf_dump(struct xe_mocs_info *info, unsigned int flags, struct xe_gt *gt, struct drm_printer *p) { … } static const struct xe_mocs_ops xehp_mocs_ops = …; static const struct xe_mocs_entry pvc_mocs_desc[] = …; static void pvc_mocs_dump(struct xe_mocs_info *info, unsigned int flags, struct xe_gt *gt, struct drm_printer *p) { … } static const struct xe_mocs_ops pvc_mocs_ops = …; static const struct xe_mocs_entry mtl_mocs_desc[] = …; static void mtl_mocs_dump(struct xe_mocs_info *info, unsigned int flags, struct xe_gt *gt, struct drm_printer *p) { … } static const struct xe_mocs_ops mtl_mocs_ops = …; static const struct xe_mocs_entry xe2_mocs_table[] = …; static void xe2_mocs_dump(struct xe_mocs_info *info, unsigned int flags, struct xe_gt *gt, struct drm_printer *p) { … } static const struct xe_mocs_ops xe2_mocs_ops = …; static unsigned int get_mocs_settings(struct xe_device *xe, struct xe_mocs_info *info) { … } /* * Get control_value from MOCS entry. If the table entry is not defined, the * settings from unused_entries_index will be returned. */ static u32 get_entry_control(const struct xe_mocs_info *info, unsigned int index) { … } static void __init_mocs_table(struct xe_gt *gt, const struct xe_mocs_info *info) { … } /* * Get l3cc_value from MOCS entry taking into account when it's not used * then if unused_entries_index is not zero then its value will be returned * otherwise I915_MOCS_PTE's value is returned in this case. */ static u16 get_entry_l3cc(const struct xe_mocs_info *info, unsigned int index) { … } static u32 l3cc_combine(u16 low, u16 high) { … } static void init_l3cc_table(struct xe_gt *gt, const struct xe_mocs_info *info) { … } void xe_mocs_init_early(struct xe_gt *gt) { … } void xe_mocs_init(struct xe_gt *gt) { … } void xe_mocs_dump(struct xe_gt *gt, struct drm_printer *p) { … } #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) #include "tests/xe_mocs.c" #endif
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