linux/drivers/gpu/drm/xe/xe_ring_ops.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2022 Intel Corporation
 */

#include "xe_ring_ops.h"

#include <generated/xe_wa_oob.h>

#include "instructions/xe_gpu_commands.h"
#include "instructions/xe_mi_commands.h"
#include "regs/xe_engine_regs.h"
#include "regs/xe_gt_regs.h"
#include "regs/xe_lrc_layout.h"
#include "xe_exec_queue_types.h"
#include "xe_gt.h"
#include "xe_lrc.h"
#include "xe_macros.h"
#include "xe_sched_job.h"
#include "xe_sriov.h"
#include "xe_vm_types.h"
#include "xe_vm.h"
#include "xe_wa.h"

/*
 * 3D-related flags that can't be set on _engines_ that lack access to the 3D
 * pipeline (i.e., CCS engines).
 */
#define PIPE_CONTROL_3D_ENGINE_FLAGS …

/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
#define PIPE_CONTROL_3D_ARCH_FLAGS …

static u32 preparser_disable(bool state)
{ … }

static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,
			      u32 *dw, int i)
{ … }

static int emit_user_interrupt(u32 *dw, int i)
{ … }

static int emit_store_imm_ggtt(u32 addr, u32 value, u32 *dw, int i)
{ … }

static int emit_flush_dw(u32 *dw, int i)
{ … }

static int emit_flush_imm_ggtt(u32 addr, u32 value, bool invalidate_tlb,
			       u32 *dw, int i)
{ … }

static int emit_bb_start(u64 batch_addr, u32 ppgtt_flag, u32 *dw, int i)
{ … }

static int emit_flush_invalidate(u32 flag, u32 *dw, int i)
{ … }

static int
emit_pipe_control(u32 *dw, int i, u32 bit_group_0, u32 bit_group_1, u32 offset, u32 value)
{ … }

static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw,
				int i)
{ … }

static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
				       u32 *dw, int i)
{ … }

static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
{ … }

static int emit_pipe_control_to_ring_end(struct xe_hw_engine *hwe, u32 *dw, int i)
{ … }

static int emit_pipe_imm_ggtt(u32 addr, u32 value, bool stall_only, u32 *dw,
			      int i)
{ … }

static u32 get_ppgtt_flag(struct xe_sched_job *job)
{ … }

static int emit_copy_timestamp(struct xe_lrc *lrc, u32 *dw, int i)
{ … }

/* for engines that don't require any special HW handling (no EUs, no aux inval, etc) */
static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc,
				    u64 batch_addr, u32 seqno)
{ … }

static bool has_aux_ccs(struct xe_device *xe)
{ … }

static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
				   u64 batch_addr, u32 seqno)
{ … }

static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
					    struct xe_lrc *lrc,
					    u64 batch_addr, u32 seqno)
{ … }

static void emit_migration_job_gen12(struct xe_sched_job *job,
				     struct xe_lrc *lrc, u32 seqno)
{ … }

static void emit_job_gen12_gsc(struct xe_sched_job *job)
{ … }

static void emit_job_gen12_copy(struct xe_sched_job *job)
{ … }

static void emit_job_gen12_video(struct xe_sched_job *job)
{ … }

static void emit_job_gen12_render_compute(struct xe_sched_job *job)
{ … }

static const struct xe_ring_ops ring_ops_gen12_gsc = …;

static const struct xe_ring_ops ring_ops_gen12_copy = …;

static const struct xe_ring_ops ring_ops_gen12_video = …;

static const struct xe_ring_ops ring_ops_gen12_render_compute = …;

const struct xe_ring_ops *
xe_ring_ops_get(struct xe_gt *gt, enum xe_engine_class class)
{ … }