// SPDX-License-Identifier: MIT /* * Copyright © 2023 Intel Corporation */ #include "xe_pat.h" #include <drm/xe_drm.h> #include "regs/xe_reg_defs.h" #include "xe_assert.h" #include "xe_device.h" #include "xe_force_wake.h" #include "xe_gt.h" #include "xe_gt_mcr.h" #include "xe_mmio.h" #include "xe_sriov.h" #define _PAT_ATS … #define _PAT_INDEX(index) … #define _PAT_PTA … #define XE2_NO_PROMOTE … #define XE2_COMP_EN … #define XE2_L3_CLOS … #define XE2_L3_POLICY … #define XE2_L4_POLICY … #define XE2_COH_MODE … #define XELPG_L4_POLICY_MASK … #define XELPG_PAT_3_UC … #define XELPG_PAT_1_WT … #define XELPG_PAT_0_WB … #define XELPG_INDEX_COH_MODE_MASK … #define XELPG_3_COH_2W … #define XELPG_2_COH_1W … #define XELPG_0_COH_NON … #define XEHPC_CLOS_LEVEL_MASK … #define XEHPC_PAT_CLOS(x) … #define XELP_MEM_TYPE_MASK … #define XELP_PAT_WB … #define XELP_PAT_WT … #define XELP_PAT_WC … #define XELP_PAT_UC … static const char *XELP_MEM_TYPE_STR_MAP[] = …; struct xe_pat_ops { … }; static const struct xe_pat_table_entry xelp_pat_table[] = …; static const struct xe_pat_table_entry xehpc_pat_table[] = …; static const struct xe_pat_table_entry xelpg_pat_table[] = …; /* * The Xe2 table is getting large/complicated so it's easier to review if * provided in a form that exactly matches the bspec's formatting. The meaning * of the fields here are: * - no_promote: 0=promotable, 1=no promote * - comp_en: 0=disable, 1=enable * - l3clos: L3 class of service (0-3) * - l3_policy: 0=WB, 1=XD ("WB - Transient Display"), 3=UC * - l4_policy: 0=WB, 1=WT, 3=UC * - coh_mode: 0=no snoop, 2=1-way coherent, 3=2-way coherent * * Reserved entries should be programmed with the maximum caching, minimum * coherency (which matches an all-0's encoding), so we can just omit them * in the table. */ #define XE2_PAT(no_promote, comp_en, l3clos, l3_policy, l4_policy, __coh_mode) … static const struct xe_pat_table_entry xe2_pat_table[] = …; /* Special PAT values programmed outside the main table */ static const struct xe_pat_table_entry xe2_pat_ats = …; static const struct xe_pat_table_entry xe2_pat_pta = …; u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index) { … } static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[], int n_entries) { … } static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry table[], int n_entries) { … } static void xelp_dump(struct xe_gt *gt, struct drm_printer *p) { … } static const struct xe_pat_ops xelp_pat_ops = …; static void xehp_dump(struct xe_gt *gt, struct drm_printer *p) { … } static const struct xe_pat_ops xehp_pat_ops = …; static void xehpc_dump(struct xe_gt *gt, struct drm_printer *p) { … } static const struct xe_pat_ops xehpc_pat_ops = …; static void xelpg_dump(struct xe_gt *gt, struct drm_printer *p) { … } /* * SAMedia register offsets are adjusted by the write methods and they target * registers that are not MCR, while for normal GT they are MCR */ static const struct xe_pat_ops xelpg_pat_ops = …; static void xe2lpg_program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[], int n_entries) { … } static void xe2lpm_program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[], int n_entries) { … } static void xe2_dump(struct xe_gt *gt, struct drm_printer *p) { … } static const struct xe_pat_ops xe2_pat_ops = …; void xe_pat_init_early(struct xe_device *xe) { … } void xe_pat_init(struct xe_gt *gt) { … } void xe_pat_dump(struct xe_gt *gt, struct drm_printer *p) { … }
Codebase Browser
linux