linux/drivers/gpu/drm/xe/xe_lmtt_ml.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2023 Intel Corporation
 */

#include <linux/align.h>
#include <linux/bitfield.h>
#include <linux/log2.h>
#include <linux/sizes.h>

#include "xe_lmtt_types.h"
#include "xe_macros.h"

/**
 * DOC: Multi-Level LMTT Structure
 *
 * LMHAW (Local Memory Host Address Width) is 48 bit (256TB)
 *
 * LMGAW (Local Memory Guest Address Width) is 48 bit (256TB)
 *
 * The following figure illustrates the structure and function of the ML LMTT::
 *
 *           LMTT L3 Directory
 *           (1 Entry per VF)                                       LMTT L1 Leaf
 *            +-----------+                                         +-----------+
 *            |           |             LMTT L2 (per VF)            |           |
 *            |           |              +-----------+              |           |
 *            |           |              |           |     index:   +===========+
 *            |           |              |           |     GDPA --> |    PTE    | => LMEM PF offset
 *            |           |              |           |     34:21    +===========+
 *            |           |    index:    |           |              |           |
 *            |           |    LMEM VF   +===========+              |           |
 *            |           |    offset -> |    PTE    |  ----------> +-----------+
 *            |           |    GAW-1:35  +===========+              /           \.
 *   index:   +===========+              |           |             /              \.
 *   VFID --> |    PDE    |  --------->  +-----------+            /                 \.
 *            +===========+             /           /            /                    \.
 *            |           |           /            /            /                       \.
 *            +-----------+  <== [LMTT Directory Ptr]          /                          \.
 *           /             \      /              /            /                             \.
 *          /                \  /               /       +-----------+-----------------+------+---+
 *         /                  /\               /        | 31:HAW-16 |        HAW-17:5 |  4:1 | 0 |
 *        /                 /    \            /         +===========+=================+======+===+
 *       /                /        \         /          |  Reserved | LMEM Page (2MB) | Rsvd | V |
 *      /                                   /           +-----------+-----------------+------+---+
 *     /                                   /
 *  +-----------+-----------------+------+---+
 *  | 63:HAW-12 |        HAW-13:4 |  3:1 | 0 |
 *  +===========+=================+======+===+
 *  |  Reserved | LMTT Ptr (64KB) | Rsvd | V |
 *  +-----------+-----------------+------+---+
 *
 */

lmtt_ml_pde_t;
lmtt_ml_pte_t;

#define LMTT_ML_HAW …

#define LMTT_ML_PDE_MAX_NUM …
#define LMTT_ML_PDE_LMTT_PTR …
#define LMTT_ML_PDE_VALID …

#define LMTT_ML_PDE_L2_SHIFT …
#define LMTT_ML_PDE_L2_MAX_NUM …

#define LMTT_ML_PTE_MAX_NUM …
#define LMTT_ML_PTE_LMEM_PAGE …
#define LMTT_ML_PTE_VALID …

static unsigned int lmtt_ml_root_pd_level(void)
{ … }

static unsigned int lmtt_ml_pte_num(unsigned int level)
{ … }

static unsigned int lmtt_ml_pte_size(unsigned int level)
{ … }

static unsigned int lmtt_ml_pte_shift(unsigned int level)
{ … }

static unsigned int lmtt_ml_pte_index(u64 addr, unsigned int level)
{ … }

static u64 lmtt_ml_pte_encode(unsigned long offset, unsigned int level)
{ … }

const struct xe_lmtt_ops lmtt_ml_ops = …;