// SPDX-License-Identifier: GPL-2.0+ /* Copyright (C) 2017-2018 Broadcom */ #ifndef V3D_REGS_H #define V3D_REGS_H #include <linux/bitops.h> #define V3D_MASK(high, low) … /* Using the GNU statement expression extension */ #define V3D_SET_FIELD(value, field) … #define V3D_GET_FIELD(word, field) … /* Hub registers for shared hardware between V3D cores. */ #define V3D_HUB_AXICFG … #define V3D_HUB_AXICFG_MAX_LEN_MASK … #define V3D_HUB_AXICFG_MAX_LEN_SHIFT … #define V3D_HUB_UIFCFG … #define V3D_HUB_IDENT0 … #define V3D_HUB_IDENT1 … #define V3D_HUB_IDENT1_WITH_MSO … #define V3D_HUB_IDENT1_WITH_TSY … #define V3D_HUB_IDENT1_WITH_TFU … #define V3D_HUB_IDENT1_WITH_L3C … #define V3D_HUB_IDENT1_NHOSTS_MASK … #define V3D_HUB_IDENT1_NHOSTS_SHIFT … #define V3D_HUB_IDENT1_NCORES_MASK … #define V3D_HUB_IDENT1_NCORES_SHIFT … #define V3D_HUB_IDENT1_REV_MASK … #define V3D_HUB_IDENT1_REV_SHIFT … #define V3D_HUB_IDENT1_TVER_MASK … #define V3D_HUB_IDENT1_TVER_SHIFT … #define V3D_HUB_IDENT2 … #define V3D_HUB_IDENT2_WITH_MMU … #define V3D_HUB_IDENT2_L3C_NKB_MASK … #define V3D_HUB_IDENT2_L3C_NKB_SHIFT … #define V3D_HUB_IDENT3 … #define V3D_HUB_IDENT3_IPREV_MASK … #define V3D_HUB_IDENT3_IPREV_SHIFT … #define V3D_HUB_IDENT3_IPIDX_MASK … #define V3D_HUB_IDENT3_IPIDX_SHIFT … #define V3D_HUB_INT_STS … #define V3D_HUB_INT_SET … #define V3D_HUB_INT_CLR … #define V3D_HUB_INT_MSK_STS … #define V3D_HUB_INT_MSK_SET … #define V3D_HUB_INT_MSK_CLR … #define V3D_V7_HUB_INT_GMPV … #define V3D_HUB_INT_MMU_WRV … #define V3D_HUB_INT_MMU_PTI … #define V3D_HUB_INT_MMU_CAP … #define V3D_HUB_INT_MSO … #define V3D_HUB_INT_TFUC … #define V3D_HUB_INT_TFUF … /* GCA registers only exist in V3D < 41 */ #define V3D_GCA_CACHE_CTRL … #define V3D_GCA_CACHE_CTRL_FLUSH … #define V3D_GCA_SAFE_SHUTDOWN … #define V3D_GCA_SAFE_SHUTDOWN_EN … #define V3D_GCA_SAFE_SHUTDOWN_ACK … #define V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED … #define V3D_TOP_GR_BRIDGE_REVISION … #define V3D_TOP_GR_BRIDGE_MAJOR_MASK … #define V3D_TOP_GR_BRIDGE_MAJOR_SHIFT … #define V3D_TOP_GR_BRIDGE_MINOR_MASK … #define V3D_TOP_GR_BRIDGE_MINOR_SHIFT … /* 7268 reset reg */ #define V3D_TOP_GR_BRIDGE_SW_INIT_0 … #define V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT … /* 7278 reset reg */ #define V3D_TOP_GR_BRIDGE_SW_INIT_1 … #define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT … #define V3D_TFU_CS(ver) … /* Stops current job, empties input fifo. */ #define V3D_TFU_CS_TFURST … #define V3D_TFU_CS_CVTCT_MASK … #define V3D_TFU_CS_CVTCT_SHIFT … #define V3D_TFU_CS_NFREE_MASK … #define V3D_TFU_CS_NFREE_SHIFT … #define V3D_TFU_CS_BUSY … #define V3D_TFU_SU(ver) … /* Interrupt when FINTTHR input slots are free (0 = disabled) */ #define V3D_TFU_SU_FINTTHR_MASK … #define V3D_TFU_SU_FINTTHR_SHIFT … /* Skips resetting the CRC at the start of CRC generation. */ #define V3D_TFU_SU_CRCCHAIN … /* skips writes, computes CRC of the image. miplevels must be 0. */ #define V3D_TFU_SU_CRC … #define V3D_TFU_SU_THROTTLE_MASK … #define V3D_TFU_SU_THROTTLE_SHIFT … #define V3D_TFU_ICFG(ver) … /* Interrupt when the conversion is complete. */ #define V3D_TFU_ICFG_IOC … /* Input Image Address */ #define V3D_TFU_IIA(ver) … /* Input Chroma Address */ #define V3D_TFU_ICA(ver) … /* Input Image Stride */ #define V3D_TFU_IIS(ver) … /* Input Image U-Plane Address */ #define V3D_TFU_IUA(ver) … /* Image output config (VD 7.x only) */ #define V3D_V7_TFU_IOC … /* Output Image Address */ #define V3D_TFU_IOA(ver) … /* Image Output Size */ #define V3D_TFU_IOS(ver) … /* TFU YUV Coefficient 0 */ #define V3D_TFU_COEF0(ver) … /* Use these regs instead of the defaults (V3D 4.x only) */ #define V3D_TFU_COEF0_USECOEF … /* TFU YUV Coefficient 1 */ #define V3D_TFU_COEF1(ver) … /* TFU YUV Coefficient 2 */ #define V3D_TFU_COEF2(ver) … /* TFU YUV Coefficient 3 */ #define V3D_TFU_COEF3(ver) … /* V3D 4.x only */ #define V3D_TFU_CRC … /* Per-MMU registers. */ #define V3D_MMUC_CONTROL … #define V3D_MMUC_CONTROL_CLEAR(ver) … #define V3D_MMUC_CONTROL_FLUSHING … #define V3D_MMUC_CONTROL_FLUSH … #define V3D_MMUC_CONTROL_ENABLE … #define V3D_MMU_CTL … #define V3D_MMU_CTL_CAP_EXCEEDED … #define V3D_MMU_CTL_CAP_EXCEEDED_ABORT … #define V3D_MMU_CTL_CAP_EXCEEDED_INT … #define V3D_MMU_CTL_CAP_EXCEEDED_EXCEPTION … #define V3D_MMU_CTL_PT_INVALID … #define V3D_MMU_CTL_PT_INVALID_ABORT … #define V3D_MMU_CTL_PT_INVALID_INT … #define V3D_MMU_CTL_PT_INVALID_EXCEPTION … #define V3D_MMU_CTL_PT_INVALID_ENABLE … #define V3D_MMU_CTL_WRITE_VIOLATION … #define V3D_MMU_CTL_WRITE_VIOLATION_ABORT … #define V3D_MMU_CTL_WRITE_VIOLATION_INT … #define V3D_MMU_CTL_WRITE_VIOLATION_EXCEPTION … #define V3D_MMU_CTL_TLB_CLEARING … #define V3D_MMU_CTL_TLB_STATS_CLEAR … #define V3D_MMU_CTL_TLB_CLEAR … #define V3D_MMU_CTL_TLB_STATS_ENABLE … #define V3D_MMU_CTL_ENABLE … #define V3D_MMU_PT_PA_BASE … #define V3D_MMU_HIT … #define V3D_MMU_MISSES … #define V3D_MMU_STALLS … #define V3D_MMU_ADDR_CAP … #define V3D_MMU_ADDR_CAP_ENABLE … #define V3D_MMU_ADDR_CAP_MPAGE_MASK … #define V3D_MMU_ADDR_CAP_MPAGE_SHIFT … #define V3D_MMU_SHOOT_DOWN … #define V3D_MMU_SHOOT_DOWN_SHOOTING … #define V3D_MMU_SHOOT_DOWN_SHOOT … #define V3D_MMU_SHOOT_DOWN_PAGE_MASK … #define V3D_MMU_SHOOT_DOWN_PAGE_SHIFT … #define V3D_MMU_BYPASS_START … #define V3D_MMU_BYPASS_END … /* AXI ID of the access that faulted */ #define V3D_MMU_VIO_ID … /* Address for illegal PTEs to return */ #define V3D_MMU_ILLEGAL_ADDR … #define V3D_MMU_ILLEGAL_ADDR_ENABLE … /* Address that faulted */ #define V3D_MMU_VIO_ADDR … #define V3D_MMU_DEBUG_INFO … #define V3D_MMU_PA_WIDTH_MASK … #define V3D_MMU_PA_WIDTH_SHIFT … #define V3D_MMU_VA_WIDTH_MASK … #define V3D_MMU_VA_WIDTH_SHIFT … #define V3D_MMU_VERSION_MASK … #define V3D_MMU_VERSION_SHIFT … /* Per-V3D-core registers */ #define V3D_CTL_IDENT0 … #define V3D_IDENT0_VER_MASK … #define V3D_IDENT0_VER_SHIFT … #define V3D_CTL_IDENT1 … /* Multiples of 1kb */ #define V3D_IDENT1_VPM_SIZE_MASK … #define V3D_IDENT1_VPM_SIZE_SHIFT … #define V3D_IDENT1_NSEM_MASK … #define V3D_IDENT1_NSEM_SHIFT … #define V3D_IDENT1_NTMU_MASK … #define V3D_IDENT1_NTMU_SHIFT … #define V3D_IDENT1_QUPS_MASK … #define V3D_IDENT1_QUPS_SHIFT … #define V3D_IDENT1_NSLC_MASK … #define V3D_IDENT1_NSLC_SHIFT … #define V3D_IDENT1_REV_MASK … #define V3D_IDENT1_REV_SHIFT … #define V3D_CTL_IDENT2 … #define V3D_IDENT2_BCG_INT … #define V3D_CTL_MISCCFG … #define V3D_CTL_MISCCFG_QRMAXCNT_MASK … #define V3D_CTL_MISCCFG_QRMAXCNT_SHIFT … #define V3D_MISCCFG_OVRTMUOUT … #define V3D_CTL_L2CACTL … #define V3D_L2CACTL_L2CCLR … #define V3D_L2CACTL_L2CDIS … #define V3D_L2CACTL_L2CENA … #define V3D_CTL_SLCACTL … #define V3D_SLCACTL_TVCCS_MASK … #define V3D_SLCACTL_TVCCS_SHIFT … #define V3D_SLCACTL_TDCCS_MASK … #define V3D_SLCACTL_TDCCS_SHIFT … #define V3D_SLCACTL_UCC_MASK … #define V3D_SLCACTL_UCC_SHIFT … #define V3D_SLCACTL_ICC_MASK … #define V3D_SLCACTL_ICC_SHIFT … #define V3D_CTL_L2TCACTL … #define V3D_L2TCACTL_TMUWCF … /* Invalidates cache lines. */ #define V3D_L2TCACTL_FLM_FLUSH … /* Removes cachelines without writing dirty lines back. */ #define V3D_L2TCACTL_FLM_CLEAR … /* Writes out dirty cachelines and marks them clean, but doesn't invalidate. */ #define V3D_L2TCACTL_FLM_CLEAN … #define V3D_L2TCACTL_FLM_MASK … #define V3D_L2TCACTL_FLM_SHIFT … #define V3D_L2TCACTL_L2TFLS … #define V3D_CTL_L2TFLSTA … #define V3D_CTL_L2TFLEND … #define V3D_CTL_INT_STS … #define V3D_CTL_INT_SET … #define V3D_CTL_INT_CLR … #define V3D_CTL_INT_MSK_STS … #define V3D_CTL_INT_MSK_SET … #define V3D_CTL_INT_MSK_CLR … #define V3D_INT_QPU_MASK … #define V3D_INT_QPU_SHIFT … #define V3D_INT_CSDDONE(ver) … #define V3D_INT_PCTR(ver) … #define V3D_INT_GMPV … #define V3D_INT_TRFB … #define V3D_INT_SPILLUSE … #define V3D_INT_OUTOMEM … #define V3D_INT_FLDONE … #define V3D_INT_FRDONE … #define V3D_CLE_CT0CS … #define V3D_CLE_CT1CS … #define V3D_CLE_CTNCS(n) … #define V3D_CLE_CT0EA … #define V3D_CLE_CT1EA … #define V3D_CLE_CTNEA(n) … #define V3D_CLE_CT0CA … #define V3D_CLE_CT1CA … #define V3D_CLE_CTNCA(n) … #define V3D_CLE_CT0RA … #define V3D_CLE_CT1RA … #define V3D_CLE_CTNRA(n) … #define V3D_CLE_CT0LC … #define V3D_CLE_CT1LC … #define V3D_CLE_CT0PC … #define V3D_CLE_CT1PC … #define V3D_CLE_PCS … #define V3D_CLE_BFC … #define V3D_CLE_RFC … #define V3D_CLE_TFBC … #define V3D_CLE_TFIT … #define V3D_CLE_CT1CFG … #define V3D_CLE_CT1TILECT … #define V3D_CLE_CT1TSKIP … #define V3D_CLE_CT1PTCT … #define V3D_CLE_CT0SYNC … #define V3D_CLE_CT1SYNC … #define V3D_CLE_CT0QTS … #define V3D_CLE_CT0QTS_ENABLE … #define V3D_CLE_CT0QBA … #define V3D_CLE_CT1QBA … #define V3D_CLE_CTNQBA(n) … #define V3D_CLE_CT0QEA … #define V3D_CLE_CT1QEA … #define V3D_CLE_CTNQEA(n) … #define V3D_CLE_CT0QMA … #define V3D_CLE_CT0QMS … #define V3D_CLE_CT1QCFG … /* If set without ETPROC, entirely skip tiles with no primitives. */ #define V3D_CLE_QCFG_ETFILT … /* If set with ETFILT, just write the clear color to tiles with no * primitives. */ #define V3D_CLE_QCFG_ETPROC … #define V3D_CLE_QCFG_ETSFLUSH … #define V3D_CLE_QCFG_MCDIS … #define V3D_PTB_BPCA … #define V3D_PTB_BPCS … #define V3D_PTB_BPOA … #define V3D_PTB_BPOS … #define V3D_PTB_BXCF … #define V3D_PTB_BXCF_RWORDERDISA … #define V3D_PTB_BXCF_CLIPDISA … #define V3D_V3_PCTR_0_EN … #define V3D_V3_PCTR_0_EN_ENABLE … #define V3D_V4_PCTR_0_EN … /* When a bit is set, resets the counter to 0. */ #define V3D_V3_PCTR_0_CLR … #define V3D_V4_PCTR_0_CLR … #define V3D_PCTR_0_OVERFLOW … #define V3D_V3_PCTR_0_PCTRS0 … #define V3D_V3_PCTR_0_PCTRS15 … #define V3D_V3_PCTR_0_PCTRSX(x) … /* Each src reg muxes four counters each. */ #define V3D_V4_PCTR_0_SRC_0_3 … #define V3D_V4_PCTR_0_SRC_28_31 … #define V3D_V4_PCTR_0_SRC_X(x) … #define V3D_PCTR_S0_MASK … #define V3D_V7_PCTR_S0_MASK … #define V3D_PCTR_S0_SHIFT … #define V3D_PCTR_S1_MASK … #define V3D_V7_PCTR_S1_MASK … #define V3D_PCTR_S1_SHIFT … #define V3D_PCTR_S2_MASK … #define V3D_V7_PCTR_S2_MASK … #define V3D_PCTR_S2_SHIFT … #define V3D_PCTR_S3_MASK … #define V3D_V7_PCTR_S3_MASK … #define V3D_PCTR_S3_SHIFT … #define V3D_PCTR_CYCLE_COUNT(ver) … /* Output values of the counters. */ #define V3D_PCTR_0_PCTR0 … #define V3D_PCTR_0_PCTR31 … #define V3D_PCTR_0_PCTRX(x) … #define V3D_GMP_STATUS(ver) … #define V3D_GMP_STATUS_GMPRST … #define V3D_GMP_STATUS_WR_COUNT_MASK … #define V3D_GMP_STATUS_WR_COUNT_SHIFT … #define V3D_GMP_STATUS_RD_COUNT_MASK … #define V3D_GMP_STATUS_RD_COUNT_SHIFT … #define V3D_GMP_STATUS_WR_ACTIVE … #define V3D_GMP_STATUS_RD_ACTIVE … #define V3D_GMP_STATUS_CFG_BUSY … #define V3D_GMP_STATUS_CNTOVF … #define V3D_GMP_STATUS_INVPROT … #define V3D_GMP_STATUS_VIO … #define V3D_GMP_CFG(ver) … #define V3D_GMP_CFG_LBURSTEN … #define V3D_GMP_CFG_PGCRSEN … #define V3D_GMP_CFG_STOP_REQ … #define V3D_GMP_CFG_PROT_ENABLE … #define V3D_GMP_VIO_ADDR(ver) … #define V3D_GMP_VIO_TYPE … #define V3D_GMP_TABLE_ADDR … #define V3D_GMP_CLEAR_LOAD … #define V3D_GMP_PRESERVE_LOAD … #define V3D_GMP_VALID_LINES … #define V3D_CSD_STATUS … #define V3D_CSD_STATUS_NUM_COMPLETED_MASK … #define V3D_CSD_STATUS_NUM_COMPLETED_SHIFT … #define V3D_CSD_STATUS_NUM_ACTIVE_MASK … #define V3D_CSD_STATUS_NUM_ACTIVE_SHIFT … #define V3D_CSD_STATUS_HAVE_CURRENT_DISPATCH … #define V3D_CSD_STATUS_HAVE_QUEUED_DISPATCH … #define V3D_CSD_QUEUED_CFG0(ver) … #define V3D_CSD_QUEUED_CFG0_NUM_WGS_X_MASK … #define V3D_CSD_QUEUED_CFG0_NUM_WGS_X_SHIFT … #define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_MASK … #define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_SHIFT … #define V3D_CSD_QUEUED_CFG1(ver) … #define V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_MASK … #define V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_SHIFT … #define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_MASK … #define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_SHIFT … #define V3D_CSD_QUEUED_CFG2(ver) … #define V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_MASK … #define V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_SHIFT … #define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_MASK … #define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_SHIFT … #define V3D_CSD_QUEUED_CFG3(ver) … #define V3D_CSD_QUEUED_CFG3_OVERLAP_WITH_PREV … #define V3D_CSD_QUEUED_CFG3_MAX_SG_ID_MASK … #define V3D_CSD_QUEUED_CFG3_MAX_SG_ID_SHIFT … #define V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_MASK … #define V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_SHIFT … #define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_MASK … #define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_SHIFT … #define V3D_CSD_QUEUED_CFG3_WG_SIZE_MASK … #define V3D_CSD_QUEUED_CFG3_WG_SIZE_SHIFT … /* Number of batches, minus 1 */ #define V3D_CSD_QUEUED_CFG4(ver) … /* Shader address, pnan, singleseg, threading, like a shader record. */ #define V3D_CSD_QUEUED_CFG5(ver) … /* Uniforms address (4 byte aligned) */ #define V3D_CSD_QUEUED_CFG6(ver) … /* V3D 7.x+ only */ #define V3D_V7_CSD_QUEUED_CFG7 … #define V3D_CSD_CURRENT_CFG0(ver) … #define V3D_CSD_CURRENT_CFG1(ver) … #define V3D_CSD_CURRENT_CFG2(ver) … #define V3D_CSD_CURRENT_CFG3(ver) … #define V3D_CSD_CURRENT_CFG4(ver) … #define V3D_CSD_CURRENT_CFG5(ver) … #define V3D_CSD_CURRENT_CFG6(ver) … /* V3D 7.x+ only */ #define V3D_V7_CSD_CURRENT_CFG7 … #define V3D_CSD_CURRENT_ID0(ver) … #define V3D_CSD_CURRENT_ID0_WG_X_MASK … #define V3D_CSD_CURRENT_ID0_WG_X_SHIFT … #define V3D_CSD_CURRENT_ID0_WG_IN_SG_MASK … #define V3D_CSD_CURRENT_ID0_WG_IN_SG_SHIFT … #define V3D_CSD_CURRENT_ID0_L_IDX_MASK … #define V3D_CSD_CURRENT_ID0_L_IDX_SHIFT … #define V3D_CSD_CURRENT_ID1(ver) … #define V3D_CSD_CURRENT_ID0_WG_Z_MASK … #define V3D_CSD_CURRENT_ID0_WG_Z_SHIFT … #define V3D_CSD_CURRENT_ID0_WG_Y_MASK … #define V3D_CSD_CURRENT_ID0_WG_Y_SHIFT … #define V3D_ERR_FDBGO … #define V3D_ERR_FDBGB … #define V3D_ERR_FDBGR … #define V3D_ERR_FDBGS … #define V3D_ERR_FDBGS_INTERPZ_IP_STALL … #define V3D_ERR_FDBGS_DEPTHO_FIFO_IP_STALL … #define V3D_ERR_FDBGS_XYNRM_IP_STALL … #define V3D_ERR_FDBGS_EZREQ_FIFO_OP_VALID … #define V3D_ERR_FDBGS_QXYF_FIFO_OP_VALID … #define V3D_ERR_FDBGS_QXYF_FIFO_OP_LAST … #define V3D_ERR_FDBGS_EZTEST_ANYQVALID … #define V3D_ERR_FDBGS_EZTEST_PASS … #define V3D_ERR_FDBGS_EZTEST_QREADY … #define V3D_ERR_FDBGS_EZTEST_VLF_OKNOVALID … #define V3D_ERR_FDBGS_EZTEST_QSTALL … #define V3D_ERR_FDBGS_EZTEST_IP_VLFSTALL … #define V3D_ERR_FDBGS_EZTEST_IP_PRSTALL … #define V3D_ERR_FDBGS_EZTEST_IP_QSTALL … #define V3D_ERR_STAT … #define V3D_ERR_L2CARE … #define V3D_ERR_VCMBE … #define V3D_ERR_VCMRE … #define V3D_ERR_VCDI … #define V3D_ERR_VCDE … #define V3D_ERR_VDWE … #define V3D_ERR_VPMEAS … #define V3D_ERR_VPMEFNA … #define V3D_ERR_VPMEWNA … #define V3D_ERR_VPMERNA … #define V3D_ERR_VPMERR … #define V3D_ERR_VPMEWR … #define V3D_ERR_VPAERRGL … #define V3D_ERR_VPAEBRGL … #define V3D_ERR_VPAERGS … #define V3D_ERR_VPAEABB … #endif /* V3D_REGS_H */
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