/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright © 2014-2015 Broadcom */ #ifndef VC4_REGS_H #define VC4_REGS_H #include <linux/bitfield.h> #include <linux/bitops.h> #define VC4_MASK(high, low) … /* Using the GNU statement expression extension */ #define VC4_SET_FIELD(value, field) … #define VC4_GET_FIELD(word, field) … #define V3D_IDENT0 … #define V3D_EXPECTED_IDENT0 … #define V3D_IDENT1 … /* Multiples of 1kb */ #define V3D_IDENT1_VPM_SIZE_MASK … #define V3D_IDENT1_VPM_SIZE_SHIFT … #define V3D_IDENT1_NSEM_MASK … #define V3D_IDENT1_NSEM_SHIFT … #define V3D_IDENT1_TUPS_MASK … #define V3D_IDENT1_TUPS_SHIFT … #define V3D_IDENT1_QUPS_MASK … #define V3D_IDENT1_QUPS_SHIFT … #define V3D_IDENT1_NSLC_MASK … #define V3D_IDENT1_NSLC_SHIFT … #define V3D_IDENT1_REV_MASK … #define V3D_IDENT1_REV_SHIFT … #define V3D_IDENT2 … #define V3D_SCRATCH … #define V3D_L2CACTL … #define V3D_L2CACTL_L2CCLR … #define V3D_L2CACTL_L2CDIS … #define V3D_L2CACTL_L2CENA … #define V3D_SLCACTL … #define V3D_SLCACTL_T1CC_MASK … #define V3D_SLCACTL_T1CC_SHIFT … #define V3D_SLCACTL_T0CC_MASK … #define V3D_SLCACTL_T0CC_SHIFT … #define V3D_SLCACTL_UCC_MASK … #define V3D_SLCACTL_UCC_SHIFT … #define V3D_SLCACTL_ICC_MASK … #define V3D_SLCACTL_ICC_SHIFT … #define V3D_INTCTL … #define V3D_INTENA … #define V3D_INTDIS … #define V3D_INT_SPILLUSE … #define V3D_INT_OUTOMEM … #define V3D_INT_FLDONE … #define V3D_INT_FRDONE … #define V3D_CT0CS … #define V3D_CT1CS … #define V3D_CTNCS(n) … #define V3D_CTRSTA … #define V3D_CTSEMA … #define V3D_CTRTSD … #define V3D_CTRUN … #define V3D_CTSUBS … #define V3D_CTERR … #define V3D_CTMODE … #define V3D_CT0EA … #define V3D_CT1EA … #define V3D_CTNEA(n) … #define V3D_CT0CA … #define V3D_CT1CA … #define V3D_CTNCA(n) … #define V3D_CT00RA0 … #define V3D_CT01RA0 … #define V3D_CTNRA0(n) … #define V3D_CT0LC … #define V3D_CT1LC … #define V3D_CTNLC(n) … #define V3D_CT0PC … #define V3D_CT1PC … #define V3D_CTNPC(n) … #define V3D_PCS … #define V3D_BMOOM … #define V3D_RMBUSY … #define V3D_RMACTIVE … #define V3D_BMBUSY … #define V3D_BMACTIVE … #define V3D_BFC … #define V3D_RFC … #define V3D_BPCA … #define V3D_BPCS … #define V3D_BPOA … #define V3D_BPOS … #define V3D_BXCF … #define V3D_SQRSV0 … #define V3D_SQRSV1 … #define V3D_SQCNTL … #define V3D_SRQPC … #define V3D_SRQUA … #define V3D_SRQUL … #define V3D_SRQCS … #define V3D_VPACNTL … #define V3D_VPMBASE … #define V3D_PCTRC … #define V3D_PCTRE … #define V3D_PCTRE_EN … #define V3D_PCTR(x) … #define V3D_PCTRS(x) … #define V3D_DBGE … #define V3D_FDBGO … #define V3D_FDBGB … #define V3D_FDBGR … #define V3D_FDBGS … #define V3D_ERRSTAT … #define PV_CONTROL … #define PV5_CONTROL_FIFO_LEVEL_HIGH_MASK … #define PV5_CONTROL_FIFO_LEVEL_HIGH_SHIFT … #define PV_CONTROL_FORMAT_MASK … #define PV_CONTROL_FORMAT_SHIFT … #define PV_CONTROL_FORMAT_24 … #define PV_CONTROL_FORMAT_DSIV_16 … #define PV_CONTROL_FORMAT_DSIC_16 … #define PV_CONTROL_FORMAT_DSIV_18 … #define PV_CONTROL_FORMAT_DSIV_24 … #define PV_CONTROL_FIFO_LEVEL_MASK … #define PV_CONTROL_FIFO_LEVEL_SHIFT … #define PV_CONTROL_CLR_AT_START … #define PV_CONTROL_TRIGGER_UNDERFLOW … #define PV_CONTROL_WAIT_HSTART … #define PV_CONTROL_PIXEL_REP_MASK … #define PV_CONTROL_PIXEL_REP_SHIFT … #define PV_CONTROL_CLK_SELECT_DSI … #define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI … #define PV_CONTROL_CLK_SELECT_VEC … #define PV_CONTROL_CLK_SELECT_MASK … #define PV_CONTROL_CLK_SELECT_SHIFT … #define PV_CONTROL_FIFO_CLR … #define PV_CONTROL_EN … #define PV_V_CONTROL … #define PV_VCONTROL_ODD_DELAY_MASK … #define PV_VCONTROL_ODD_DELAY_SHIFT … #define PV_VCONTROL_ODD_FIRST … #define PV_VCONTROL_INTERLACE … #define PV_VCONTROL_DSI … #define PV_VCONTROL_COMMAND … #define PV_VCONTROL_CONTINUOUS … #define PV_VCONTROL_VIDEN … #define PV_VSYNCD_EVEN … #define PV_HORZA … #define PV_HORZA_HBP_MASK … #define PV_HORZA_HBP_SHIFT … #define PV_HORZA_HSYNC_MASK … #define PV_HORZA_HSYNC_SHIFT … #define PV_HORZB … #define PV_HORZB_HFP_MASK … #define PV_HORZB_HFP_SHIFT … #define PV_HORZB_HACTIVE_MASK … #define PV_HORZB_HACTIVE_SHIFT … #define PV_VERTA … #define PV_VERTA_VBP_MASK … #define PV_VERTA_VBP_SHIFT … #define PV_VERTA_VSYNC_MASK … #define PV_VERTA_VSYNC_SHIFT … #define PV_VERTB … #define PV_VERTB_VFP_MASK … #define PV_VERTB_VFP_SHIFT … #define PV_VERTB_VACTIVE_MASK … #define PV_VERTB_VACTIVE_SHIFT … #define PV_VERTA_EVEN … #define PV_VERTB_EVEN … #define PV_INTEN … #define PV_INTSTAT … #define PV_INT_VID_IDLE … #define PV_INT_VFP_END … #define PV_INT_VFP_START … #define PV_INT_VACT_START … #define PV_INT_VBP_START … #define PV_INT_VSYNC_START … #define PV_INT_HFP_START … #define PV_INT_HACT_START … #define PV_INT_HBP_START … #define PV_INT_HSYNC_START … #define PV_STAT … #define PV_HACT_ACT … #define PV_MUX_CFG … #define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_MASK … #define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT … #define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP … #define SCALER_CHANNELS_COUNT … #define SCALER_DISPCTRL … /* Global register for clock gating the HVS */ #define SCALER_DISPCTRL_ENABLE … #define SCALER_DISPCTRL_PANIC0_MASK … #define SCALER_DISPCTRL_PANIC0_SHIFT … #define SCALER_DISPCTRL_PANIC1_MASK … #define SCALER_DISPCTRL_PANIC1_SHIFT … #define SCALER_DISPCTRL_PANIC2_MASK … #define SCALER_DISPCTRL_PANIC2_SHIFT … #define SCALER_DISPCTRL_DSP3_MUX_MASK … #define SCALER_DISPCTRL_DSP3_MUX_SHIFT … /* Enables Display 0 short line and underrun contribution to * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are * always enabled. */ #define SCALER_DISPCTRL_DSPEISLUR(x) … #define SCALER5_DISPCTRL_DSPEISLUR(x) … /* Enables Display 0 end-of-line-N contribution to * SCALER_DISPSTAT_IRQDISP0 */ #define SCALER_DISPCTRL_DSPEIEOLN(x) … #define SCALER5_DISPCTRL_DSPEIEOLN(x) … /* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */ #define SCALER_DISPCTRL_DSPEIEOF(x) … #define SCALER5_DISPCTRL_DSPEIEOF(x) … #define SCALER5_DISPCTRL_DSPEIVST(x) … #define SCALER_DISPCTRL_SLVRDEIRQ … #define SCALER_DISPCTRL_SLVWREIRQ … #define SCALER5_DISPCTRL_SLVEIRQ … #define SCALER_DISPCTRL_DMAEIRQ … /* Enables interrupt generation on the enabled EOF/EOLN/EISLUR * bits and short frames.. */ #define SCALER_DISPCTRL_DISPEIRQ(x) … /* Enables interrupt generation on scaler profiler interrupt. */ #define SCALER_DISPCTRL_SCLEIRQ … #define SCALER_DISPSTAT … #define SCALER_DISPSTAT_RESP_MASK … #define SCALER_DISPSTAT_RESP_SHIFT … #define SCALER_DISPSTAT_RESP_OKAY … #define SCALER_DISPSTAT_RESP_EXOKAY … #define SCALER_DISPSTAT_RESP_SLVERR … #define SCALER_DISPSTAT_RESP_DECERR … #define SCALER_DISPSTAT_COBLOW(x) … /* Set when the DISPEOLN line is done compositing. */ #define SCALER_DISPSTAT_EOLN(x) … /* Set when VSTART is seen but there are still pixels in the current * output line. */ #define SCALER_DISPSTAT_ESFRAME(x) … /* Set when HSTART is seen but there are still pixels in the current * output line. */ #define SCALER_DISPSTAT_ESLINE(x) … /* Set when the downstream tries to read from the display FIFO * while it's empty. */ #define SCALER_DISPSTAT_EUFLOW(x) … /* Set when the display mode changes from RUN to EOF */ #define SCALER_DISPSTAT_EOF(x) … #define SCALER_DISPSTAT_IRQMASK(x) … /* Set on AXI invalid DMA ID error. */ #define SCALER_DISPSTAT_DMA_ERROR … /* Set on AXI slave read decode error */ #define SCALER_DISPSTAT_IRQSLVRD … /* Set on AXI slave write decode error */ #define SCALER_DISPSTAT_IRQSLVWR … /* Set when SCALER_DISPSTAT_DMA_ERROR is set, or * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY. */ #define SCALER_DISPSTAT_IRQDMA … /* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their * corresponding interrupt bit is enabled in DISPCTRL. */ #define SCALER_DISPSTAT_IRQDISP(x) … /* On read, the profiler interrupt. On write, clear *all* interrupt bits. */ #define SCALER_DISPSTAT_IRQSCL … #define SCALER_DISPID … #define SCALER_DISPECTRL … #define SCALER_DISPECTRL_DSP2_MUX_SHIFT … #define SCALER_DISPECTRL_DSP2_MUX_MASK … #define SCALER_DISPPROF … #define SCALER_DISPDITHER … #define SCALER_DISPDITHER_DSP5_MUX_SHIFT … #define SCALER_DISPDITHER_DSP5_MUX_MASK … #define SCALER_DISPEOLN … #define SCALER_DISPEOLN_DSP4_MUX_SHIFT … #define SCALER_DISPEOLN_DSP4_MUX_MASK … #define SCALER_DISPLIST0 … #define SCALER_DISPLIST1 … #define SCALER_DISPLIST2 … #define SCALER_DISPLSTAT … #define SCALER_DISPLISTX(x) … #define SCALER_DISPLACT0 … #define SCALER_DISPLACT1 … #define SCALER_DISPLACT2 … #define SCALER_DISPLACTX(x) … #define SCALER_DISPCTRL0 … #define SCALER_DISPCTRLX_ENABLE … #define SCALER_DISPCTRLX_RESET … /* Generates a single frame when VSTART is seen and stops at the last * pixel read from the FIFO. */ #define SCALER_DISPCTRLX_ONESHOT … /* Processes a single context in the dlist and then task switch, * instead of an entire line. */ #define SCALER_DISPCTRLX_ONECTX … /* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */ #define SCALER_DISPCTRLX_FIFO32 … /* Turns on output to the DISPSLAVE register instead of the normal * FIFO. */ #define SCALER_DISPCTRLX_FIFOREG … #define SCALER_DISPCTRLX_WIDTH_MASK … #define SCALER_DISPCTRLX_WIDTH_SHIFT … #define SCALER_DISPCTRLX_HEIGHT_MASK … #define SCALER_DISPCTRLX_HEIGHT_SHIFT … #define SCALER5_DISPCTRLX_WIDTH_MASK … #define SCALER5_DISPCTRLX_WIDTH_SHIFT … /* Generates a single frame when VSTART is seen and stops at the last * pixel read from the FIFO. */ #define SCALER5_DISPCTRLX_ONESHOT … /* Processes a single context in the dlist and then task switch, * instead of an entire line. */ #define SCALER5_DISPCTRLX_ONECTX_MASK … #define SCALER5_DISPCTRLX_ONECTX_SHIFT … #define SCALER5_DISPCTRLX_HEIGHT_MASK … #define SCALER5_DISPCTRLX_HEIGHT_SHIFT … #define SCALER_DISPBKGND0 … #define SCALER_DISPBKGND_AUTOHS … #define SCALER5_DISPBKGND_BCK2BCK … #define SCALER_DISPBKGND_INTERLACE … #define SCALER_DISPBKGND_GAMMA … #define SCALER_DISPBKGND_TESTMODE_MASK … #define SCALER_DISPBKGND_TESTMODE_SHIFT … /* Enables filling the scaler line with the RGB value in the low 24 * bits before compositing. Costs cycles, so should be skipped if * opaque display planes will cover everything. */ #define SCALER_DISPBKGND_FILL … #define SCALER_DISPSTAT0 … #define SCALER_DISPSTATX_MODE_MASK … #define SCALER_DISPSTATX_MODE_SHIFT … #define SCALER_DISPSTATX_MODE_DISABLED … #define SCALER_DISPSTATX_MODE_INIT … #define SCALER_DISPSTATX_MODE_RUN … #define SCALER_DISPSTATX_MODE_EOF … #define SCALER_DISPSTATX_FULL … #define SCALER_DISPSTATX_EMPTY … #define SCALER_DISPSTATX_LINE_MASK … #define SCALER_DISPSTATX_LINE_SHIFT … #define SCALER_DISPBASE0 … /* Last pixel in the COB (display FIFO memory) allocated to this HVS * channel. Must be 4-pixel aligned (and thus 4 pixels less than the * next COB base). */ #define SCALER_DISPBASEX_TOP_MASK … #define SCALER_DISPBASEX_TOP_SHIFT … /* First pixel in the COB (display FIFO memory) allocated to this HVS * channel. Must be 4-pixel aligned. */ #define SCALER_DISPBASEX_BASE_MASK … #define SCALER_DISPBASEX_BASE_SHIFT … #define SCALER_DISPCTRL1 … #define SCALER_DISPBKGND1 … #define SCALER_DISPBKGNDX(x) … #define SCALER_DISPSTAT1 … #define SCALER_DISPSTAT1_FRCNT0_MASK … #define SCALER_DISPSTAT1_FRCNT0_SHIFT … #define SCALER_DISPSTAT1_FRCNT1_MASK … #define SCALER_DISPSTAT1_FRCNT1_SHIFT … #define SCALER_DISPSTATX(x) … #define SCALER_DISPBASE1 … #define SCALER_DISPBASEX(x) … #define SCALER_DISPCTRL2 … #define SCALER_DISPCTRLX(x) … #define SCALER_DISPBKGND2 … #define SCALER_DISPSTAT2 … #define SCALER_DISPSTAT2_FRCNT2_MASK … #define SCALER_DISPSTAT2_FRCNT2_SHIFT … #define SCALER_DISPBASE2 … #define SCALER_DISPALPHA2 … #define SCALER_GAMADDR … #define SCALER_GAMADDR_AUTOINC … /* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma * enabled. */ #define SCALER_GAMADDR_SRAMENB … #define SCALER_OLEDOFFS … /* Clamps R to [16,235] and G/B to [16,240]. */ #define SCALER_OLEDOFFS_YUVCLAMP … /* Chooses which display FIFO the matrix applies to. */ #define SCALER_OLEDOFFS_DISPFIFO_MASK … #define SCALER_OLEDOFFS_DISPFIFO_SHIFT … #define SCALER_OLEDOFFS_DISPFIFO_DISABLED … #define SCALER_OLEDOFFS_DISPFIFO_0 … #define SCALER_OLEDOFFS_DISPFIFO_1 … #define SCALER_OLEDOFFS_DISPFIFO_2 … /* Offsets are 8-bit 2s-complement. */ #define SCALER_OLEDOFFS_RED_MASK … #define SCALER_OLEDOFFS_RED_SHIFT … #define SCALER_OLEDOFFS_GREEN_MASK … #define SCALER_OLEDOFFS_GREEN_SHIFT … #define SCALER_OLEDOFFS_BLUE_MASK … #define SCALER_OLEDOFFS_BLUE_SHIFT … /* The coefficients are S0.9 fractions. */ #define SCALER_OLEDCOEF0 … #define SCALER_OLEDCOEF0_B_TO_R_MASK … #define SCALER_OLEDCOEF0_B_TO_R_SHIFT … #define SCALER_OLEDCOEF0_B_TO_G_MASK … #define SCALER_OLEDCOEF0_B_TO_G_SHIFT … #define SCALER_OLEDCOEF0_B_TO_B_MASK … #define SCALER_OLEDCOEF0_B_TO_B_SHIFT … #define SCALER_OLEDCOEF1 … #define SCALER_OLEDCOEF1_G_TO_R_MASK … #define SCALER_OLEDCOEF1_G_TO_R_SHIFT … #define SCALER_OLEDCOEF1_G_TO_G_MASK … #define SCALER_OLEDCOEF1_G_TO_G_SHIFT … #define SCALER_OLEDCOEF1_G_TO_B_MASK … #define SCALER_OLEDCOEF1_G_TO_B_SHIFT … #define SCALER_OLEDCOEF2 … #define SCALER_OLEDCOEF2_R_TO_R_MASK … #define SCALER_OLEDCOEF2_R_TO_R_SHIFT … #define SCALER_OLEDCOEF2_R_TO_G_MASK … #define SCALER_OLEDCOEF2_R_TO_G_SHIFT … #define SCALER_OLEDCOEF2_R_TO_B_MASK … #define SCALER_OLEDCOEF2_R_TO_B_SHIFT … /* Slave addresses for DMAing from HVS composition output to other * devices. The top bits are valid only in !FIFO32 mode. */ #define SCALER_DISPSLAVE0 … #define SCALER_DISPSLAVE1 … #define SCALER_DISPSLAVE2 … #define SCALER_DISPSLAVE_ISSUE_VSTART … #define SCALER_DISPSLAVE_ISSUE_HSTART … /* Set when the current line has been read and an HSTART is required. */ #define SCALER_DISPSLAVE_EOL … /* Set when the display FIFO is empty. */ #define SCALER_DISPSLAVE_EMPTY … /* Set when there is RGB data ready to read. */ #define SCALER_DISPSLAVE_VALID … #define SCALER_DISPSLAVE_RGB_MASK … #define SCALER_DISPSLAVE_RGB_SHIFT … #define SCALER_GAMDATA … #define SCALER_DLIST_START … #define SCALER_DLIST_SIZE … #define SCALER5_DLIST_START … #define VC4_HDMI_SW_RESET_FORMAT_DETECT … #define VC4_HDMI_SW_RESET_HDMI … #define VC4_HDMI_HOTPLUG_CONNECTED … #define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE … #define VC4_HDMI_MAI_CONFIG_BIT_REVERSE … #define VC4_HDMI_MAI_CHANNEL_MASK_MASK … #define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT … #define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT … #define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS … #define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT … #define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME … #define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK … #define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT … /* If set, then multichannel, otherwise 2 channel. */ #define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT … /* If set, then AUDIO_LAYOUT overrides audio_cea_mask */ #define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT … #define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK … #define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT … #define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_MASK … #define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_SHIFT … enum { … }; #define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_MASK … #define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_SHIFT … enum { … }; #define VC4_HDMI_RAM_PACKET_ENABLE … /* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead * of pixel clock. */ #define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS … /* When set, no CRP packets will be sent. */ #define VC4_HDMI_CRP_CFG_DISABLE … /* If set, generates CTS values based on N, audio clock, and video * clock. N must be divisible by 128. */ #define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN … #define VC4_HDMI_CRP_CFG_N_MASK … #define VC4_HDMI_CRP_CFG_N_SHIFT … #define VC4_HDMI_HORZA_VPOS … #define VC4_HDMI_HORZA_HPOS … /* Horizontal active pixels (hdisplay). */ #define VC4_HDMI_HORZA_HAP_MASK … #define VC4_HDMI_HORZA_HAP_SHIFT … /* Horizontal back porch (htotal - hsync_end). */ #define VC4_HDMI_HORZB_HBP_MASK … #define VC4_HDMI_HORZB_HBP_SHIFT … /* Horizontal sync pulse (hsync_end - hsync_start). */ #define VC4_HDMI_HORZB_HSP_MASK … #define VC4_HDMI_HORZB_HSP_SHIFT … /* Horizontal front porch (hsync_start - hdisplay). */ #define VC4_HDMI_HORZB_HFP_MASK … #define VC4_HDMI_HORZB_HFP_SHIFT … #define VC4_HDMI_FIFO_CTL_RECENTER_DONE … #define VC4_HDMI_FIFO_CTL_USE_EMPTY … #define VC4_HDMI_FIFO_CTL_ON_VB … #define VC4_HDMI_FIFO_CTL_RECENTER … #define VC4_HDMI_FIFO_CTL_FIFO_RESET … #define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK … #define VC4_HDMI_FIFO_CTL_INV_CLK_XFR … #define VC4_HDMI_FIFO_CTL_CAPTURE_PTR … #define VC4_HDMI_FIFO_CTL_USE_FULL … #define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N … #define VC4_HDMI_FIFO_VALID_WRITE_MASK … #define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT … #define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS … #define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT … #define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE … #define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI … /* Vertical sync pulse (vsync_end - vsync_start). */ #define VC4_HDMI_VERTA_VSP_MASK … #define VC4_HDMI_VERTA_VSP_SHIFT … /* Vertical front porch (vsync_start - vdisplay). */ #define VC4_HDMI_VERTA_VFP_MASK … #define VC4_HDMI_VERTA_VFP_SHIFT … /* Vertical active lines (vdisplay). */ #define VC4_HDMI_VERTA_VAL_MASK … #define VC4_HDMI_VERTA_VAL_SHIFT … /* Vertical sync pulse offset (for interlaced) */ #define VC4_HDMI_VERTB_VSPO_MASK … #define VC4_HDMI_VERTB_VSPO_SHIFT … /* Vertical pack porch (vtotal - vsync_end). */ #define VC4_HDMI_VERTB_VBP_MASK … #define VC4_HDMI_VERTB_VBP_SHIFT … /* Set when the transmission has ended. */ #define VC4_HDMI_CEC_TX_EOM … /* If set, transmission was acked on the 1st or 2nd attempt (only one * retry is attempted). If in continuous mode, this means TX needs to * be filled if !TX_EOM. */ #define VC4_HDMI_CEC_TX_STATUS_GOOD … #define VC4_HDMI_CEC_RX_EOM … #define VC4_HDMI_CEC_RX_STATUS_GOOD … /* Number of bytes received for the message. */ #define VC4_HDMI_CEC_REC_WRD_CNT_MASK … #define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT … /* Sets continuous receive mode. Generates interrupt after each 8 * bytes to signal that RX_DATA should be consumed, and at RX_EOM. * * If disabled, maximum 16 bytes will be received (including header), * and interrupt at RX_EOM. Later bytes will be acked but not put * into the RX_DATA. */ #define VC4_HDMI_CEC_RX_CONTINUE … #define VC4_HDMI_CEC_TX_CONTINUE … /* Set this after a CEC interrupt. */ #define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF … /* Starts a TX. Will wait for appropriate idel time before CEC * activity. Must be cleared in between transmits. */ #define VC4_HDMI_CEC_START_XMIT_BEGIN … #define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK … #define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT … /* Device's CEC address */ #define VC4_HDMI_CEC_ADDR_MASK … #define VC4_HDMI_CEC_ADDR_SHIFT … /* Divides off of HSM clock to generate CEC bit clock. */ /* With the current defaults the CEC bit clock is 40 kHz = 25 usec */ #define VC4_HDMI_CEC_DIV_CLK_CNT_MASK … #define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT … /* Set these fields to how many bit clock cycles get to that many * microseconds. */ #define VC4_HDMI_CEC_CNT_TO_1500_US_MASK … #define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT … #define VC4_HDMI_CEC_CNT_TO_1300_US_MASK … #define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT … #define VC4_HDMI_CEC_CNT_TO_800_US_MASK … #define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT … #define VC4_HDMI_CEC_CNT_TO_600_US_MASK … #define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT … #define VC4_HDMI_CEC_CNT_TO_400_US_MASK … #define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT … #define VC4_HDMI_CEC_CNT_TO_2750_US_MASK … #define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT … #define VC4_HDMI_CEC_CNT_TO_2400_US_MASK … #define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT … #define VC4_HDMI_CEC_CNT_TO_2050_US_MASK … #define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT … #define VC4_HDMI_CEC_CNT_TO_1700_US_MASK … #define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT … #define VC4_HDMI_CEC_CNT_TO_4300_US_MASK … #define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT … #define VC4_HDMI_CEC_CNT_TO_3900_US_MASK … #define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT … #define VC4_HDMI_CEC_CNT_TO_3600_US_MASK … #define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT … #define VC4_HDMI_CEC_CNT_TO_3500_US_MASK … #define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT … #define VC4_HDMI_CEC_TX_SW_RESET … #define VC4_HDMI_CEC_RX_SW_RESET … #define VC4_HDMI_CEC_PAD_SW_RESET … #define VC4_HDMI_CEC_MUX_TP_OUT_CEC … #define VC4_HDMI_CEC_RX_CEC_INT … #define VC4_HDMI_CEC_CLK_PRELOAD_MASK … #define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT … #define VC4_HDMI_CEC_CNT_TO_4700_US_MASK … #define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT … #define VC4_HDMI_CEC_CNT_TO_4500_US_MASK … #define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT … #define VC4_HDMI_TX_PHY_RNG_PWRDN … #define VC4_HDMI_CPU_CEC … #define VC4_HDMI_CPU_HOTPLUG … /* Debug: Current receive value on the CEC pad. */ #define VC4_HD_CECRXD … /* Debug: Override CEC output to 0. */ #define VC4_HD_CECOVR … #define VC4_HD_M_REGISTER_FILE_STANDBY … #define VC4_HD_M_RAM_STANDBY … #define VC4_HD_M_SW_RST … #define VC4_HD_M_ENABLE … /* Set when audio stream is received at a slower rate than the * sampling period, so MAI fifo goes empty. Write 1 to clear. */ #define VC4_HD_MAI_CTL_DLATE … #define VC4_HD_MAI_CTL_BUSY … #define VC4_HD_MAI_CTL_CHALIGN … #define VC4_HD_MAI_CTL_WHOLSMP … #define VC4_HD_MAI_CTL_FULL … #define VC4_HD_MAI_CTL_EMPTY … #define VC4_HD_MAI_CTL_FLUSH … /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing * through. */ #define VC4_HD_MAI_CTL_PAREN … #define VC4_HD_MAI_CTL_CHNUM_MASK … #define VC4_HD_MAI_CTL_CHNUM_SHIFT … #define VC4_HD_MAI_CTL_ENABLE … /* Underflow error status bit, write 1 to clear. */ #define VC4_HD_MAI_CTL_ERRORE … /* Overflow error status bit, write 1 to clear. */ #define VC4_HD_MAI_CTL_ERRORF … /* Single-shot reset bit. Read value is undefined. */ #define VC4_HD_MAI_CTL_RESET … #define VC4_HD_MAI_THR_PANICHIGH_MASK … #define VC4_HD_MAI_THR_PANICHIGH_SHIFT … #define VC4_HD_MAI_THR_PANICLOW_MASK … #define VC4_HD_MAI_THR_PANICLOW_SHIFT … #define VC4_HD_MAI_THR_DREQHIGH_MASK … #define VC4_HD_MAI_THR_DREQHIGH_SHIFT … #define VC4_HD_MAI_THR_DREQLOW_MASK … #define VC4_HD_MAI_THR_DREQLOW_SHIFT … /* Divider from HDMI HSM clock to MAI serial clock. Sampling period * converges to N / (M + 1) cycles. */ #define VC4_HD_MAI_SMP_N_MASK … #define VC4_HD_MAI_SMP_N_SHIFT … #define VC4_HD_MAI_SMP_M_MASK … #define VC4_HD_MAI_SMP_M_SHIFT … #define VC4_HD_VID_CTL_ENABLE … #define VC4_HD_VID_CTL_UNDERFLOW_ENABLE … #define VC4_HD_VID_CTL_FRAME_COUNTER_RESET … #define VC4_HD_VID_CTL_VSYNC_LOW … #define VC4_HD_VID_CTL_HSYNC_LOW … #define VC4_HD_VID_CTL_CLRSYNC … #define VC4_HD_VID_CTL_CLRRGB … #define VC4_HD_VID_CTL_BLANKPIX … #define VC4_HD_CSC_CTL_ORDER_MASK … #define VC4_HD_CSC_CTL_ORDER_SHIFT … #define VC4_HD_CSC_CTL_ORDER_RGB … #define VC4_HD_CSC_CTL_ORDER_BGR … #define VC4_HD_CSC_CTL_ORDER_BRG … #define VC4_HD_CSC_CTL_ORDER_GRB … #define VC4_HD_CSC_CTL_ORDER_GBR … #define VC4_HD_CSC_CTL_ORDER_RBG … #define VC4_HD_CSC_CTL_PADMSB … #define VC4_HD_CSC_CTL_MODE_MASK … #define VC4_HD_CSC_CTL_MODE_SHIFT … #define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB … #define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB … #define VC4_HD_CSC_CTL_MODE_CUSTOM … #define VC4_HD_CSC_CTL_RGB2YCC … #define VC4_HD_CSC_CTL_ENABLE … #define VC5_MT_CP_CSC_CTL_USE_444_TO_422 … #define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_MASK … #define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD … #define VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION … #define VC5_MT_CP_CSC_CTL_ENABLE … #define VC5_MT_CP_CSC_CTL_MODE_MASK … #define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_MASK … #define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE … #define VC4_DVP_HT_CLOCK_STOP_PIXEL … #define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_MASK … #define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY … /* HVS display list information. */ #define HVS_BOOTLOADER_DLIST_END … enum hvs_pixel_format { … }; /* Note: the LSB is the rightmost character shown. Only valid for * HVS_PIXEL_FORMAT_RGB8888, not RGB888. */ /* For modes 332, 4444, 555, 5551, 6666, 8888, 10:10:10:2 */ #define HVS_PIXEL_ORDER_RGBA … #define HVS_PIXEL_ORDER_BGRA … #define HVS_PIXEL_ORDER_ARGB … #define HVS_PIXEL_ORDER_ABGR … /* For modes 666 and 888 (4 & 5) */ #define HVS_PIXEL_ORDER_XBRG … #define HVS_PIXEL_ORDER_XRBG … #define HVS_PIXEL_ORDER_XRGB … #define HVS_PIXEL_ORDER_XBGR … /* For YCbCr modes (8-12, and 17) */ #define HVS_PIXEL_ORDER_XYCBCR … #define HVS_PIXEL_ORDER_XYCRCB … #define HVS_PIXEL_ORDER_YXCBCR … #define HVS_PIXEL_ORDER_YXCRCB … #define SCALER_CTL0_END … #define SCALER_CTL0_VALID … #define SCALER_CTL0_SIZE_MASK … #define SCALER_CTL0_SIZE_SHIFT … #define SCALER_CTL0_TILING_MASK … #define SCALER_CTL0_TILING_SHIFT … #define SCALER_CTL0_TILING_LINEAR … #define SCALER_CTL0_TILING_64B … #define SCALER_CTL0_TILING_128B … #define SCALER_CTL0_TILING_256B_OR_T … #define SCALER_CTL0_ALPHA_MASK … #define SCALER_CTL0_HFLIP … #define SCALER_CTL0_VFLIP … #define SCALER_CTL0_KEY_MODE_MASK … #define SCALER_CTL0_KEY_MODE_SHIFT … #define SCALER_CTL0_KEY_DISABLED … #define SCALER_CTL0_KEY_LUMA_OR_COMMON_RGB … #define SCALER_CTL0_KEY_MATCH … #define SCALER_CTL0_KEY_REPLACE … #define SCALER_CTL0_ORDER_MASK … #define SCALER_CTL0_ORDER_SHIFT … #define SCALER_CTL0_RGBA_EXPAND_MASK … #define SCALER_CTL0_RGBA_EXPAND_SHIFT … #define SCALER_CTL0_RGBA_EXPAND_ZERO … #define SCALER_CTL0_RGBA_EXPAND_LSB … #define SCALER_CTL0_RGBA_EXPAND_MSB … #define SCALER_CTL0_RGBA_EXPAND_ROUND … #define SCALER5_CTL0_ALPHA_EXPAND … #define SCALER5_CTL0_RGB_EXPAND … #define SCALER_CTL0_SCL1_MASK … #define SCALER_CTL0_SCL1_SHIFT … #define SCALER_CTL0_SCL0_MASK … #define SCALER_CTL0_SCL0_SHIFT … #define SCALER_CTL0_SCL_H_PPF_V_PPF … #define SCALER_CTL0_SCL_H_TPZ_V_PPF … #define SCALER_CTL0_SCL_H_PPF_V_TPZ … #define SCALER_CTL0_SCL_H_TPZ_V_TPZ … #define SCALER_CTL0_SCL_H_PPF_V_NONE … #define SCALER_CTL0_SCL_H_NONE_V_PPF … #define SCALER_CTL0_SCL_H_NONE_V_TPZ … #define SCALER_CTL0_SCL_H_TPZ_V_NONE … /* Set to indicate no scaling. */ #define SCALER_CTL0_UNITY … #define SCALER5_CTL0_UNITY … #define SCALER_CTL0_PIXEL_FORMAT_MASK … #define SCALER_CTL0_PIXEL_FORMAT_SHIFT … #define SCALER5_CTL0_PIXEL_FORMAT_MASK … #define SCALER_POS0_FIXED_ALPHA_MASK … #define SCALER_POS0_FIXED_ALPHA_SHIFT … #define SCALER_POS0_START_Y_MASK … #define SCALER_POS0_START_Y_SHIFT … #define SCALER_POS0_START_X_MASK … #define SCALER_POS0_START_X_SHIFT … #define SCALER5_POS0_START_Y_MASK … #define SCALER5_POS0_START_Y_SHIFT … #define SCALER5_POS0_START_X_MASK … #define SCALER5_POS0_START_X_SHIFT … #define SCALER5_POS0_VFLIP … #define SCALER5_POS0_HFLIP … #define SCALER5_CTL2_ALPHA_MODE_MASK … #define SCALER5_CTL2_ALPHA_MODE_SHIFT … #define SCALER5_CTL2_ALPHA_MODE_PIPELINE … #define SCALER5_CTL2_ALPHA_MODE_FIXED … #define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO … #define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 … #define SCALER5_CTL2_ALPHA_PREMULT … #define SCALER5_CTL2_ALPHA_MIX … #define SCALER5_CTL2_ALPHA_LOC … #define SCALER5_CTL2_MAP_SEL_MASK … #define SCALER5_CTL2_MAP_SEL_SHIFT … #define SCALER5_CTL2_GAMMA … #define SCALER5_CTL2_ALPHA_MASK … #define SCALER5_CTL2_ALPHA_SHIFT … #define SCALER_POS1_SCL_HEIGHT_MASK … #define SCALER_POS1_SCL_HEIGHT_SHIFT … #define SCALER_POS1_SCL_WIDTH_MASK … #define SCALER_POS1_SCL_WIDTH_SHIFT … #define SCALER5_POS1_SCL_HEIGHT_MASK … #define SCALER5_POS1_SCL_HEIGHT_SHIFT … #define SCALER5_POS1_SCL_WIDTH_MASK … #define SCALER5_POS1_SCL_WIDTH_SHIFT … #define SCALER_POS2_ALPHA_MODE_MASK … #define SCALER_POS2_ALPHA_MODE_SHIFT … #define SCALER_POS2_ALPHA_MODE_PIPELINE … #define SCALER_POS2_ALPHA_MODE_FIXED … #define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO … #define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 … #define SCALER_POS2_ALPHA_PREMULT … #define SCALER_POS2_ALPHA_MIX … #define SCALER_POS2_HEIGHT_MASK … #define SCALER_POS2_HEIGHT_SHIFT … #define SCALER_POS2_WIDTH_MASK … #define SCALER_POS2_WIDTH_SHIFT … #define SCALER5_POS2_HEIGHT_MASK … #define SCALER5_POS2_HEIGHT_SHIFT … #define SCALER5_POS2_WIDTH_MASK … #define SCALER5_POS2_WIDTH_SHIFT … /* Color Space Conversion words. Some values are S2.8 signed * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1, * 0x2: 2, 0x3: -1} */ /* bottom 8 bits of S2.8 contribution of Cr to Blue */ #define SCALER_CSC0_COEF_CR_BLU_MASK … #define SCALER_CSC0_COEF_CR_BLU_SHIFT … /* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */ #define SCALER_CSC0_COEF_YY_OFS_MASK … #define SCALER_CSC0_COEF_YY_OFS_SHIFT … /* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */ #define SCALER_CSC0_COEF_CB_OFS_MASK … #define SCALER_CSC0_COEF_CB_OFS_SHIFT … /* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */ #define SCALER_CSC0_COEF_CR_OFS_MASK … #define SCALER_CSC0_COEF_CR_OFS_SHIFT … #define SCALER_CSC0_ITR_R_601_5 … #define SCALER_CSC0_ITR_R_709_3 … #define SCALER_CSC0_ITR_R_2020 … #define SCALER_CSC0_JPEG_JFIF … #define SCALER_CSC0_ITR_R_709_3_FR … #define SCALER_CSC0_ITR_R_2020_FR … /* S2.8 contribution of Cb to Green */ #define SCALER_CSC1_COEF_CB_GRN_MASK … #define SCALER_CSC1_COEF_CB_GRN_SHIFT … /* S2.8 contribution of Cr to Green */ #define SCALER_CSC1_COEF_CR_GRN_MASK … #define SCALER_CSC1_COEF_CR_GRN_SHIFT … /* S2.8 contribution of Y to all of RGB */ #define SCALER_CSC1_COEF_YY_ALL_MASK … #define SCALER_CSC1_COEF_YY_ALL_SHIFT … /* top 2 bits of S2.8 contribution of Cr to Blue */ #define SCALER_CSC1_COEF_CR_BLU_MASK … #define SCALER_CSC1_COEF_CR_BLU_SHIFT … #define SCALER_CSC1_ITR_R_601_5 … #define SCALER_CSC1_ITR_R_709_3 … #define SCALER_CSC1_ITR_R_2020 … #define SCALER_CSC1_JPEG_JFIF … #define SCALER_CSC1_ITR_R_709_3_FR … #define SCALER_CSC1_ITR_R_2020_FR … /* S2.8 contribution of Cb to Red */ #define SCALER_CSC2_COEF_CB_RED_MASK … #define SCALER_CSC2_COEF_CB_RED_SHIFT … /* S2.8 contribution of Cr to Red */ #define SCALER_CSC2_COEF_CR_RED_MASK … #define SCALER_CSC2_COEF_CR_RED_SHIFT … /* S2.8 contribution of Cb to Blue */ #define SCALER_CSC2_COEF_CB_BLU_MASK … #define SCALER_CSC2_COEF_CB_BLU_SHIFT … #define SCALER_CSC2_ITR_R_601_5 … #define SCALER_CSC2_ITR_R_709_3 … #define SCALER_CSC2_ITR_R_2020 … #define SCALER_CSC2_JPEG_JFIF … #define SCALER_CSC2_ITR_R_709_3_FR … #define SCALER_CSC2_ITR_R_2020_FR … #define SCALER_TPZ0_VERT_RECALC … #define SCALER_TPZ0_SCALE_MASK … #define SCALER_TPZ0_SCALE_SHIFT … #define SCALER_TPZ0_IPHASE_MASK … #define SCALER_TPZ0_IPHASE_SHIFT … #define SCALER_TPZ1_RECIP_MASK … #define SCALER_TPZ1_RECIP_SHIFT … /* Skips interpolating coefficients to 64 phases, so just 8 are used. * Required for nearest neighbor. */ #define SCALER_PPF_NOINTERP … /* Replaes the highest valued coefficient with one that makes all 4 * sum to unity. */ #define SCALER_PPF_AGC … #define SCALER_PPF_SCALE_MASK … #define SCALER_PPF_SCALE_SHIFT … #define SCALER_PPF_IPHASE_MASK … #define SCALER_PPF_IPHASE_SHIFT … #define SCALER_PPF_KERNEL_OFFSET_MASK … #define SCALER_PPF_KERNEL_OFFSET_SHIFT … #define SCALER_PPF_KERNEL_UNCACHED … /* PITCH0/1/2 fields for raster. */ #define SCALER_SRC_PITCH_MASK … #define SCALER_SRC_PITCH_SHIFT … /* PITCH0/1/2 fields for tiled (SAND). */ #define SCALER_TILE_SKIP_0_MASK … #define SCALER_TILE_SKIP_0_SHIFT … #define SCALER_TILE_HEIGHT_MASK … #define SCALER_TILE_HEIGHT_SHIFT … /* Common PITCH0 fields */ #define SCALER_PITCH0_SINK_PIX_MASK … #define SCALER_PITCH0_SINK_PIX_SHIFT … /* PITCH0 fields for T-tiled. */ #define SCALER_PITCH0_TILE_WIDTH_L_MASK … #define SCALER_PITCH0_TILE_WIDTH_L_SHIFT … #define SCALER_PITCH0_TILE_LINE_DIR … #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR … /* Y offset within a tile. */ #define SCALER_PITCH0_TILE_Y_OFFSET_MASK … #define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT … #define SCALER_PITCH0_TILE_WIDTH_R_MASK … #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT … #endif /* VC4_REGS_H */
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