// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2016 Broadcom */ /** * DOC: VC4 SDTV module * * The VEC encoder generates PAL or NTSC composite video output. * * TV mode selection is done by an atomic property on the encoder, * because a drm_mode_modeinfo is insufficient to distinguish between * PAL and PAL-M or NTSC and NTSC-J. */ #include <drm/drm_atomic_helper.h> #include <drm/drm_drv.h> #include <drm/drm_edid.h> #include <drm/drm_panel.h> #include <drm/drm_probe_helper.h> #include <drm/drm_simple_kms_helper.h> #include <linux/clk.h> #include <linux/component.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include "vc4_drv.h" #include "vc4_regs.h" /* WSE Registers */ #define VEC_WSE_RESET … #define VEC_WSE_CONTROL … #define VEC_WSE_WSS_ENABLE … #define VEC_WSE_WSS_DATA … #define VEC_WSE_VPS_DATA1 … #define VEC_WSE_VPS_CONTROL … /* VEC Registers */ #define VEC_REVID … #define VEC_CONFIG0 … #define VEC_CONFIG0_YDEL_MASK … #define VEC_CONFIG0_YDEL(x) … #define VEC_CONFIG0_CDEL_MASK … #define VEC_CONFIG0_CDEL(x) … #define VEC_CONFIG0_SECAM_STD … #define VEC_CONFIG0_PBPR_FIL … #define VEC_CONFIG0_CHROMA_GAIN_MASK … #define VEC_CONFIG0_CHROMA_GAIN_UNITY … #define VEC_CONFIG0_CHROMA_GAIN_1_32 … #define VEC_CONFIG0_CHROMA_GAIN_1_16 … #define VEC_CONFIG0_CHROMA_GAIN_1_8 … #define VEC_CONFIG0_CBURST_GAIN_MASK … #define VEC_CONFIG0_CBURST_GAIN_UNITY … #define VEC_CONFIG0_CBURST_GAIN_1_128 … #define VEC_CONFIG0_CBURST_GAIN_1_64 … #define VEC_CONFIG0_CBURST_GAIN_1_32 … #define VEC_CONFIG0_CHRBW1 … #define VEC_CONFIG0_CHRBW0 … #define VEC_CONFIG0_SYNCDIS … #define VEC_CONFIG0_BURDIS … #define VEC_CONFIG0_CHRDIS … #define VEC_CONFIG0_PDEN … #define VEC_CONFIG0_YCDELAY … #define VEC_CONFIG0_RAMPEN … #define VEC_CONFIG0_YCDIS … #define VEC_CONFIG0_STD_MASK … #define VEC_CONFIG0_NTSC_STD … #define VEC_CONFIG0_PAL_BDGHI_STD … #define VEC_CONFIG0_PAL_M_STD … #define VEC_CONFIG0_PAL_N_STD … #define VEC_SCHPH … #define VEC_SOFT_RESET … #define VEC_CLMP0_START … #define VEC_CLMP0_END … /* * These set the color subcarrier frequency * if VEC_CONFIG1_CUSTOM_FREQ is enabled. * * VEC_FREQ1_0 contains the most significant 16-bit half-word, * VEC_FREQ3_2 contains the least significant 16-bit half-word. * 0x80000000 seems to be equivalent to the pixel clock * (which itself is the VEC clock divided by 8). * * Reference values (with the default pixel clock of 13.5 MHz): * * NTSC (3579545.[45] Hz) - 0x21F07C1F * PAL (4433618.75 Hz) - 0x2A098ACB * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3 * PAL-N (3582056.25 Hz) - 0x21F69446 * * NOTE: For SECAM, it is used as the Dr center frequency, * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not; * that is specified as 4406250 Hz, which corresponds to 0x29C71C72. */ #define VEC_FREQ3_2 … #define VEC_FREQ1_0 … #define VEC_CONFIG1 … #define VEC_CONFIG_VEC_RESYNC_OFF … #define VEC_CONFIG_RGB219 … #define VEC_CONFIG_CBAR_EN … #define VEC_CONFIG_TC_OBB … #define VEC_CONFIG1_OUTPUT_MODE_MASK … #define VEC_CONFIG1_C_Y_CVBS … #define VEC_CONFIG1_CVBS_Y_C … #define VEC_CONFIG1_PR_Y_PB … #define VEC_CONFIG1_RGB … #define VEC_CONFIG1_Y_C_CVBS … #define VEC_CONFIG1_C_CVBS_Y … #define VEC_CONFIG1_C_CVBS_CVBS … #define VEC_CONFIG1_DIS_CHR … #define VEC_CONFIG1_DIS_LUMA … #define VEC_CONFIG1_YCBCR_IN … #define VEC_CONFIG1_DITHER_TYPE_LFSR … #define VEC_CONFIG1_DITHER_TYPE_COUNTER … #define VEC_CONFIG1_DITHER_EN … #define VEC_CONFIG1_CYDELAY … #define VEC_CONFIG1_LUMADIS … #define VEC_CONFIG1_COMPDIS … #define VEC_CONFIG1_CUSTOM_FREQ … #define VEC_CONFIG2 … #define VEC_CONFIG2_PROG_SCAN … #define VEC_CONFIG2_SYNC_ADJ_MASK … #define VEC_CONFIG2_SYNC_ADJ(x) … #define VEC_CONFIG2_PBPR_EN … #define VEC_CONFIG2_UV_DIG_DIS … #define VEC_CONFIG2_RGB_DIG_DIS … #define VEC_CONFIG2_TMUX_MASK … #define VEC_CONFIG2_TMUX_DRIVE0 … #define VEC_CONFIG2_TMUX_RG_COMP … #define VEC_CONFIG2_TMUX_UV_YC … #define VEC_CONFIG2_TMUX_SYNC_YC … #define VEC_INTERRUPT_CONTROL … #define VEC_INTERRUPT_STATUS … /* * Db center frequency for SECAM; the clock for this is the same as for * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency. * * This is specified as 4250000 Hz, which corresponds to 0x284BDA13. * That is also the default value, so no need to set it explicitly. */ #define VEC_FCW_SECAM_B … #define VEC_SECAM_GAIN_VAL … #define VEC_CONFIG3 … #define VEC_CONFIG3_HORIZ_LEN_STD … #define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF … #define VEC_CONFIG3_SHAPE_NON_LINEAR … #define VEC_STATUS0 … #define VEC_MASK0 … #define VEC_CFG … #define VEC_CFG_SG_MODE_MASK … #define VEC_CFG_SG_MODE(x) … #define VEC_CFG_SG_EN … #define VEC_CFG_VEC_EN … #define VEC_CFG_MB_EN … #define VEC_CFG_ENABLE … #define VEC_CFG_TB_EN … #define VEC_DAC_TEST … #define VEC_DAC_CONFIG … #define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) … #define VEC_DAC_CONFIG_DRIVER_CTRL(x) … #define VEC_DAC_CONFIG_DAC_CTRL(x) … #define VEC_DAC_MISC … #define VEC_DAC_MISC_VCD_CTRL_MASK … #define VEC_DAC_MISC_VCD_CTRL(x) … #define VEC_DAC_MISC_VID_ACT … #define VEC_DAC_MISC_VCD_PWRDN … #define VEC_DAC_MISC_BIAS_PWRDN … #define VEC_DAC_MISC_DAC_PWRDN … #define VEC_DAC_MISC_LDO_PWRDN … #define VEC_DAC_MISC_DAC_RST_N … struct vc4_vec_variant { … }; /* General VEC hardware state. */ struct vc4_vec { … }; #define VEC_READ(offset) … #define VEC_WRITE(offset, val) … #define encoder_to_vc4_vec(_encoder) … #define connector_to_vc4_vec(_connector) … enum vc4_vec_tv_mode_id { … }; struct vc4_vec_tv_mode { … }; static const struct debugfs_reg32 vec_regs[] = …; static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = …; static inline const struct vc4_vec_tv_mode * vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal) { … } static const struct drm_prop_enum_list legacy_tv_mode_names[] = …; static enum drm_connector_status vc4_vec_connector_detect(struct drm_connector *connector, bool force) { … } static void vc4_vec_connector_reset(struct drm_connector *connector) { … } static int vc4_vec_connector_set_property(struct drm_connector *connector, struct drm_connector_state *state, struct drm_property *property, uint64_t val) { … } static int vc4_vec_connector_get_property(struct drm_connector *connector, const struct drm_connector_state *state, struct drm_property *property, uint64_t *val) { … } static const struct drm_connector_funcs vc4_vec_connector_funcs = …; static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = …; static int vc4_vec_connector_init(struct drm_device *dev, struct vc4_vec *vec) { … } static void vc4_vec_encoder_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) { … } static void vc4_vec_encoder_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) { … } static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { … } static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = …; static int vc4_vec_late_register(struct drm_encoder *encoder) { … } static const struct drm_encoder_funcs vc4_vec_encoder_funcs = …; static const struct vc4_vec_variant bcm2835_vec_variant = …; static const struct vc4_vec_variant bcm2711_vec_variant = …; static const struct of_device_id vc4_vec_dt_match[] = …; static int vc4_vec_bind(struct device *dev, struct device *master, void *data) { … } static const struct component_ops vc4_vec_ops = …; static int vc4_vec_dev_probe(struct platform_device *pdev) { … } static void vc4_vec_dev_remove(struct platform_device *pdev) { … } struct platform_driver vc4_vec_driver = …;
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