vc4_plane.c | Explore in Territory

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 Broadcom
 */

/**
 * DOC: VC4 plane module
 *
 * Each DRM plane is a layer of pixels being scanned out by the HVS.
 *
 * At atomic modeset check time, we compute the HVS display element
 * state that would be necessary for displaying the plane (giving us a
 * chance to figure out if a plane configuration is invalid), then at
 * atomic flush time the CRTC will ask us to write our element state
 * into the region of the HVS that it has allocated for us.
 */

#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_atomic_uapi.h>
#include <drm/drm_blend.h>
#include <drm/drm_drv.h>
#include <drm/drm_fb_dma_helper.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_framebuffer.h>
#include <drm/drm_gem_atomic_helper.h>

#include "uapi/drm/vc4_drm.h"

#include "vc4_drv.h"
#include "vc4_regs.h"

static const struct hvs_format { … } hvs_formats[] = …;

static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
{ … }

static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
{ … }

static bool plane_enabled(struct drm_plane_state *state)
{ … }

static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
{ … }

static void vc4_plane_destroy_state(struct drm_plane *plane,
				    struct drm_plane_state *state)
{ … }

/* Called during init to allocate the plane's atomic state. */
static void vc4_plane_reset(struct drm_plane *plane)
{ … }

static void vc4_dlist_counter_increment(struct vc4_plane_state *vc4_state)
{ … }

static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
{ … }

/* Returns the scl0/scl1 field based on whether the dimensions need to
 * be up/down/non-scaled.
 *
 * This is a replication of a table from the spec.
 */
static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
{ … }

static int vc4_plane_margins_adj(struct drm_plane_state *pstate)
{ … }

static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
{ … }

static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
{ … }

static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
{ … }

static u32 vc4_lbm_size(struct drm_plane_state *state)
{ … }

static void vc4_write_scaling_parameters(struct drm_plane_state *state,
					 int channel)
{ … }

static void vc4_plane_calc_load(struct drm_plane_state *state)
{ … }

static int vc4_plane_allocate_lbm(struct drm_plane_state *state)
{ … }

/*
 * The colorspace conversion matrices are held in 3 entries in the dlist.
 * Create an array of them, with entries for each full and limited mode, and
 * each supported colorspace.
 */
static const u32 colorspace_coeffs[2][DRM_COLOR_ENCODING_MAX][3] = …;

static u32 vc4_hvs4_get_alpha_blend_mode(struct drm_plane_state *state)
{ … }

static u32 vc4_hvs5_get_alpha_blend_mode(struct drm_plane_state *state)
{ … }

/* Writes out a full display list for an active plane to the plane's
 * private dlist state.
 */
static int vc4_plane_mode_set(struct drm_plane *plane,
			      struct drm_plane_state *state)
{ … }

/* If a modeset involves changing the setup of a plane, the atomic
 * infrastructure will call this to validate a proposed plane setup.
 * However, if a plane isn't getting updated, this (and the
 * corresponding vc4_plane_atomic_update) won't get called.  Thus, we
 * compute the dlist here and have all active plane dlists get updated
 * in the CRTC's flush.
 */
static int vc4_plane_atomic_check(struct drm_plane *plane,
				  struct drm_atomic_state *state)
{ … }

static void vc4_plane_atomic_update(struct drm_plane *plane,
				    struct drm_atomic_state *state)
{ … }

u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
{ … }

u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
{ … }

/* Updates the plane to immediately (well, once the FIFO needs
 * refilling) scan out from at a new framebuffer.
 */
void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
{ … }

static void vc4_plane_atomic_async_update(struct drm_plane *plane,
					  struct drm_atomic_state *state)
{ … }

static int vc4_plane_atomic_async_check(struct drm_plane *plane,
					struct drm_atomic_state *state)
{ … }

static int vc4_prepare_fb(struct drm_plane *plane,
			  struct drm_plane_state *state)
{ … }

static void vc4_cleanup_fb(struct drm_plane *plane,
			   struct drm_plane_state *state)
{ … }

static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = …;

static const struct drm_plane_helper_funcs vc5_plane_helper_funcs = …;

static bool vc4_format_mod_supported(struct drm_plane *plane,
				     uint32_t format,
				     uint64_t modifier)
{ … }

static const struct drm_plane_funcs vc4_plane_funcs = …;

struct drm_plane *vc4_plane_init(struct drm_device *dev,
				 enum drm_plane_type type,
				 uint32_t possible_crtcs)
{ … }

#define VC4_NUM_OVERLAY_PLANES …

int vc4_plane_create_additional_planes(struct drm_device *drm)
{ … }
linux/drivers/gpu/drm/vc4/vc4_plane.c
