// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2015 Broadcom * Copyright (c) 2014 The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark <[email protected]> */ #include "vc4_hdmi.h" #include "vc4_regs.h" #include "vc4_hdmi_regs.h" #define VC4_HDMI_TX_PHY_RESET_CTL_PLL_RESETB … #define VC4_HDMI_TX_PHY_RESET_CTL_PLLDIV_RESETB … #define VC4_HDMI_TX_PHY_RESET_CTL_TX_CK_RESET … #define VC4_HDMI_TX_PHY_RESET_CTL_TX_2_RESET … #define VC4_HDMI_TX_PHY_RESET_CTL_TX_1_RESET … #define VC4_HDMI_TX_PHY_RESET_CTL_TX_0_RESET … #define VC4_HDMI_TX_PHY_POWERDOWN_CTL_RNDGEN_PWRDN … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_PREEMP_SHIFT … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_PREEMP_MASK … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_MAINDRV_SHIFT … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_MAINDRV_MASK … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_PREEMP_SHIFT … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_PREEMP_MASK … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_MAINDRV_SHIFT … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_MAINDRV_MASK … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_PREEMP_SHIFT … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_PREEMP_MASK … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_MAINDRV_SHIFT … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_MAINDRV_MASK … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_PREEMP_SHIFT … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_PREEMP_MASK … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_SHIFT … #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_MASK … #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA2_SHIFT … #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA2_MASK … #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA1_SHIFT … #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA1_MASK … #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA0_SHIFT … #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA0_MASK … #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_SHIFT … #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_MASK … #define VC4_HDMI_TX_PHY_CTL_2_VCO_GAIN_SHIFT … #define VC4_HDMI_TX_PHY_CTL_2_VCO_GAIN_MASK … #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA2_SHIFT … #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA2_MASK … #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA1_SHIFT … #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA1_MASK … #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA0_SHIFT … #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA0_MASK … #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_SHIFT … #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_MASK … #define VC4_HDMI_TX_PHY_CTL_3_RP_SHIFT … #define VC4_HDMI_TX_PHY_CTL_3_RP_MASK … #define VC4_HDMI_TX_PHY_CTL_3_RZ_SHIFT … #define VC4_HDMI_TX_PHY_CTL_3_RZ_MASK … #define VC4_HDMI_TX_PHY_CTL_3_CP1_SHIFT … #define VC4_HDMI_TX_PHY_CTL_3_CP1_MASK … #define VC4_HDMI_TX_PHY_CTL_3_CP_SHIFT … #define VC4_HDMI_TX_PHY_CTL_3_CP_MASK … #define VC4_HDMI_TX_PHY_CTL_3_CZ_SHIFT … #define VC4_HDMI_TX_PHY_CTL_3_CZ_MASK … #define VC4_HDMI_TX_PHY_CTL_3_ICP_SHIFT … #define VC4_HDMI_TX_PHY_CTL_3_ICP_MASK … #define VC4_HDMI_TX_PHY_PLL_CTL_0_MASH11_MODE … #define VC4_HDMI_TX_PHY_PLL_CTL_0_VC_RANGE_EN … #define VC4_HDMI_TX_PHY_PLL_CTL_0_EMULATE_VC_LOW … #define VC4_HDMI_TX_PHY_PLL_CTL_0_EMULATE_VC_HIGH … #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL_SHIFT … #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL_MASK … #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_FB_DIV2 … #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_POST_DIV2 … #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_CONT_EN … #define VC4_HDMI_TX_PHY_PLL_CTL_0_ENA_VCO_CLK … #define VC4_HDMI_TX_PHY_PLL_CTL_1_CPP_SHIFT … #define VC4_HDMI_TX_PHY_PLL_CTL_1_CPP_MASK … #define VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY_SHIFT … #define VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY_MASK … #define VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_ENABLE … #define VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL_SHIFT … #define VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL_MASK … #define VC4_HDMI_TX_PHY_CLK_DIV_VCO_SHIFT … #define VC4_HDMI_TX_PHY_CLK_DIV_VCO_MASK … #define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_SHIFT … #define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_MASK … #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL_MASK … #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL_SHIFT … #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL_MASK … #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL_SHIFT … #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL_MASK … #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL_SHIFT … #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL_MASK … #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL_SHIFT … #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_MASK … #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_SHIFT … #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_MASK … #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_SHIFT … #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD_MASK … #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD_SHIFT … #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD_MASK … #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD_SHIFT … #define VC4_HDMI_RM_CONTROL_EN_FREEZE_COUNTERS … #define VC4_HDMI_RM_CONTROL_EN_LOAD_INTEGRATOR … #define VC4_HDMI_RM_CONTROL_FREE_RUN … #define VC4_HDMI_RM_OFFSET_ONLY … #define VC4_HDMI_RM_OFFSET_OFFSET_SHIFT … #define VC4_HDMI_RM_OFFSET_OFFSET_MASK … #define VC4_HDMI_RM_FORMAT_SHIFT_SHIFT … #define VC4_HDMI_RM_FORMAT_SHIFT_MASK … #define OSCILLATOR_FREQUENCY … void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_connector_state *conn_state) { … } void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi) { … } void vc4_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi) { … } void vc4_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi) { … } static unsigned long long phy_get_vco_freq(unsigned long long clock, u8 *vco_sel, u8 *vco_div) { … } static u8 phy_get_cp_current(unsigned long vco_freq) { … } static u32 phy_get_rm_offset(unsigned long long vco_freq) { … } static u8 phy_get_vco_gain(unsigned long long vco_freq) { … } struct phy_lane_settings { … }; struct phy_settings { … }; static const struct phy_settings vc5_hdmi_phy_settings[] = …; static const struct phy_settings *phy_get_settings(unsigned long long tmds_rate) { … } static const struct phy_lane_settings * phy_get_channel_settings(enum vc4_hdmi_phy_channel chan, unsigned long long tmds_rate) { … } static void vc5_hdmi_reset_phy(struct vc4_hdmi *vc4_hdmi) { … } void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_connector_state *conn_state) { … } void vc5_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi) { … } void vc5_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi) { … } void vc5_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi) { … }
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