linux/drivers/gpu/drm/vc4/vc4_qpu_defines.h

/*
 * Copyright © 2014 Broadcom
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#ifndef VC4_QPU_DEFINES_H
#define VC4_QPU_DEFINES_H

enum qpu_op_add {};

enum qpu_op_mul {};

enum qpu_raddr {};

enum qpu_waddr {};

enum qpu_sig_bits {};

enum qpu_mux {};

enum qpu_cond {};

enum qpu_pack_mul {};

enum qpu_pack_a {};

enum qpu_unpack_r4 {};

#define QPU_MASK(high, low)

#define QPU_GET_FIELD(word, field)

#define QPU_SIG_SHIFT
#define QPU_SIG_MASK

#define QPU_UNPACK_SHIFT
#define QPU_UNPACK_MASK

/**
 * If set, the pack field means PACK_MUL or R4 packing, instead of normal
 * regfile a packing.
 */
#define QPU_PM

#define QPU_PACK_SHIFT
#define QPU_PACK_MASK

#define QPU_COND_ADD_SHIFT
#define QPU_COND_ADD_MASK
#define QPU_COND_MUL_SHIFT
#define QPU_COND_MUL_MASK

#define QPU_BRANCH_COND_SHIFT
#define QPU_BRANCH_COND_MASK

#define QPU_BRANCH_REL
#define QPU_BRANCH_REG

#define QPU_BRANCH_RADDR_A_SHIFT
#define QPU_BRANCH_RADDR_A_MASK

#define QPU_SF

#define QPU_WADDR_ADD_SHIFT
#define QPU_WADDR_ADD_MASK
#define QPU_WADDR_MUL_SHIFT
#define QPU_WADDR_MUL_MASK

#define QPU_OP_MUL_SHIFT
#define QPU_OP_MUL_MASK

#define QPU_RADDR_A_SHIFT
#define QPU_RADDR_A_MASK
#define QPU_RADDR_B_SHIFT
#define QPU_RADDR_B_MASK
#define QPU_SMALL_IMM_SHIFT
#define QPU_SMALL_IMM_MASK

#define QPU_ADD_A_SHIFT
#define QPU_ADD_A_MASK
#define QPU_ADD_B_SHIFT
#define QPU_ADD_B_MASK
#define QPU_MUL_A_SHIFT
#define QPU_MUL_A_MASK
#define QPU_MUL_B_SHIFT
#define QPU_MUL_B_MASK

#define QPU_WS

#define QPU_OP_ADD_SHIFT
#define QPU_OP_ADD_MASK

#define QPU_LOAD_IMM_SHIFT
#define QPU_LOAD_IMM_MASK

#define QPU_BRANCH_TARGET_SHIFT
#define QPU_BRANCH_TARGET_MASK

#endif /* VC4_QPU_DEFINES_H */