/* * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * */ #ifndef __NVKM_CLK_GK20A_H__ #define __NVKM_CLK_GK20A_H__ #define KHZ … #define MHZ … #define MASK(w) … #define GK20A_CLK_GPC_MDIV … #define SYS_GPCPLL_CFG_BASE … #define GPCPLL_CFG … #define GPCPLL_CFG_ENABLE … #define GPCPLL_CFG_IDDQ … #define GPCPLL_CFG_LOCK_DET_OFF … #define GPCPLL_CFG_LOCK … #define GPCPLL_CFG2 … #define GPCPLL_CFG2_SETUP2_SHIFT … #define GPCPLL_CFG2_PLL_STEPA_SHIFT … #define GPCPLL_CFG3 … #define GPCPLL_CFG3_VCO_CTRL_SHIFT … #define GPCPLL_CFG3_VCO_CTRL_WIDTH … #define GPCPLL_CFG3_VCO_CTRL_MASK … #define GPCPLL_CFG3_PLL_STEPB_SHIFT … #define GPCPLL_CFG3_PLL_STEPB_WIDTH … #define GPCPLL_COEFF … #define GPCPLL_COEFF_M_SHIFT … #define GPCPLL_COEFF_M_WIDTH … #define GPCPLL_COEFF_N_SHIFT … #define GPCPLL_COEFF_N_WIDTH … #define GPCPLL_COEFF_N_MASK … #define GPCPLL_COEFF_P_SHIFT … #define GPCPLL_COEFF_P_WIDTH … #define GPCPLL_NDIV_SLOWDOWN … #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT … #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT … #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT … #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT … #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT … #define GPC_BCAST_GPCPLL_CFG_BASE … #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG … #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT … #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK … #define SEL_VCO … #define SEL_VCO_GPC2CLK_OUT_SHIFT … #define GPC2CLK_OUT … #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH … #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT … #define GPC2CLK_OUT_SDIV14_INDIV4_MODE … #define GPC2CLK_OUT_VCODIV_WIDTH … #define GPC2CLK_OUT_VCODIV_SHIFT … #define GPC2CLK_OUT_VCODIV1 … #define GPC2CLK_OUT_VCODIV2 … #define GPC2CLK_OUT_VCODIV_MASK … #define GPC2CLK_OUT_BYPDIV_WIDTH … #define GPC2CLK_OUT_BYPDIV_SHIFT … #define GPC2CLK_OUT_BYPDIV31 … #define GPC2CLK_OUT_INIT_MASK … #define GPC2CLK_OUT_INIT_VAL … /* All frequencies in Khz */ struct gk20a_clk_pllg_params { … }; struct gk20a_pll { … }; struct gk20a_clk { … }; #define gk20a_clk(p) … u32 gk20a_pllg_calc_rate(struct gk20a_clk *, struct gk20a_pll *); int gk20a_pllg_calc_mnp(struct gk20a_clk *, unsigned long, struct gk20a_pll *); void gk20a_pllg_read_mnp(struct gk20a_clk *, struct gk20a_pll *); void gk20a_pllg_write_mnp(struct gk20a_clk *, const struct gk20a_pll *); static inline bool gk20a_pllg_is_enabled(struct gk20a_clk *clk) { … } static inline u32 gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll) { … } int gk20a_clk_ctor(struct nvkm_device *, enum nvkm_subdev_type, int, const struct nvkm_clk_func *, const struct gk20a_clk_pllg_params *, struct gk20a_clk *); void gk20a_clk_fini(struct nvkm_clk *); int gk20a_clk_read(struct nvkm_clk *, enum nv_clk_src); int gk20a_clk_calc(struct nvkm_clk *, struct nvkm_cstate *); int gk20a_clk_prog(struct nvkm_clk *); void gk20a_clk_tidy(struct nvkm_clk *); int gk20a_clk_setup_slide(struct gk20a_clk *); #endif
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