/* * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include <subdev/clk.h> #include <subdev/volt.h> #include <subdev/timer.h> #include <core/device.h> #include <core/tegra.h> #include "priv.h" #include "gk20a.h" #define GPCPLL_CFG_SYNC_MODE … #define BYPASSCTRL_SYS … #define BYPASSCTRL_SYS_GPCPLL_SHIFT … #define BYPASSCTRL_SYS_GPCPLL_WIDTH … #define GPCPLL_CFG2_SDM_DIN_SHIFT … #define GPCPLL_CFG2_SDM_DIN_WIDTH … #define GPCPLL_CFG2_SDM_DIN_MASK … #define GPCPLL_CFG2_SDM_DIN_NEW_SHIFT … #define GPCPLL_CFG2_SDM_DIN_NEW_WIDTH … #define GPCPLL_CFG2_SDM_DIN_NEW_MASK … #define GPCPLL_CFG2_SETUP2_SHIFT … #define GPCPLL_CFG2_PLL_STEPA_SHIFT … #define GPCPLL_DVFS0 … #define GPCPLL_DVFS0_DFS_COEFF_SHIFT … #define GPCPLL_DVFS0_DFS_COEFF_WIDTH … #define GPCPLL_DVFS0_DFS_COEFF_MASK … #define GPCPLL_DVFS0_DFS_DET_MAX_SHIFT … #define GPCPLL_DVFS0_DFS_DET_MAX_WIDTH … #define GPCPLL_DVFS0_DFS_DET_MAX_MASK … #define GPCPLL_DVFS1 … #define GPCPLL_DVFS1_DFS_EXT_DET_SHIFT … #define GPCPLL_DVFS1_DFS_EXT_DET_WIDTH … #define GPCPLL_DVFS1_DFS_EXT_STRB_SHIFT … #define GPCPLL_DVFS1_DFS_EXT_STRB_WIDTH … #define GPCPLL_DVFS1_DFS_EXT_CAL_SHIFT … #define GPCPLL_DVFS1_DFS_EXT_CAL_WIDTH … #define GPCPLL_DVFS1_DFS_EXT_SEL_SHIFT … #define GPCPLL_DVFS1_DFS_EXT_SEL_WIDTH … #define GPCPLL_DVFS1_DFS_CTRL_SHIFT … #define GPCPLL_DVFS1_DFS_CTRL_WIDTH … #define GPCPLL_DVFS1_EN_SDM_SHIFT … #define GPCPLL_DVFS1_EN_SDM_WIDTH … #define GPCPLL_DVFS1_EN_SDM_BIT … #define GPCPLL_DVFS1_EN_DFS_SHIFT … #define GPCPLL_DVFS1_EN_DFS_WIDTH … #define GPCPLL_DVFS1_EN_DFS_BIT … #define GPCPLL_DVFS1_EN_DFS_CAL_SHIFT … #define GPCPLL_DVFS1_EN_DFS_CAL_WIDTH … #define GPCPLL_DVFS1_EN_DFS_CAL_BIT … #define GPCPLL_DVFS1_DFS_CAL_DONE_SHIFT … #define GPCPLL_DVFS1_DFS_CAL_DONE_WIDTH … #define GPCPLL_DVFS1_DFS_CAL_DONE_BIT … #define GPC_BCAST_GPCPLL_DVFS2 … #define GPC_BCAST_GPCPLL_DVFS2_DFS_EXT_STROBE_BIT … #define GPCPLL_CFG3_PLL_DFS_TESTOUT_SHIFT … #define GPCPLL_CFG3_PLL_DFS_TESTOUT_WIDTH … #define DFS_DET_RANGE … #define SDM_DIN_RANGE … struct gm20b_clk_dvfs_params { … }; static const struct gm20b_clk_dvfs_params gm20b_dvfs_params = …; /* * base.n is now the *integer* part of the N factor. * sdm_din contains n's decimal part. */ struct gm20b_pll { … }; struct gm20b_clk_dvfs { … }; struct gm20b_clk { … }; #define gm20b_clk(p) … static u32 pl_to_div(u32 pl) { … } static u32 div_to_pl(u32 div) { … } static const struct gk20a_clk_pllg_params gm20b_pllg_params = …; static void gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) { … } static void gm20b_pllg_write_mnp(struct gm20b_clk *clk, const struct gm20b_pll *pll) { … } /* * Determine DFS_COEFF for the requested voltage. Always select external * calibration override equal to the voltage, and set maximum detection * limit "0" (to make sure that PLL output remains under F/V curve when * voltage increases). */ static void gm20b_dvfs_calc_det_coeff(struct gm20b_clk *clk, s32 uv, struct gm20b_clk_dvfs *dvfs) { … } /* * Solve equation for integer and fractional part of the effective NDIV: * * n_eff = n_int + 1/2 + (SDM_DIN / 2^(SDM_DIN_RANGE + 1)) + * (DVFS_COEFF * DVFS_DET_DELTA) / 2^DFS_DET_RANGE * * The SDM_DIN LSB is finally shifted out, since it is not accessible by sw. */ static void gm20b_dvfs_calc_ndiv(struct gm20b_clk *clk, u32 n_eff, u32 *n_int, u32 *sdm_din) { … } static int gm20b_pllg_slide(struct gm20b_clk *clk, u32 n) { … } static int gm20b_pllg_enable(struct gm20b_clk *clk) { … } static void gm20b_pllg_disable(struct gm20b_clk *clk) { … } static int gm20b_pllg_program_mnp(struct gm20b_clk *clk, const struct gk20a_pll *pll) { … } static int gm20b_pllg_program_mnp_slide(struct gm20b_clk *clk, const struct gk20a_pll *pll) { … } static int gm20b_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) { … } /* * Compute PLL parameters that are always safe for the current voltage */ static void gm20b_dvfs_calc_safe_pll(struct gm20b_clk *clk, struct gk20a_pll *pll) { … } static void gm20b_dvfs_program_coeff(struct gm20b_clk *clk, u32 coeff) { … } static void gm20b_dvfs_program_ext_cal(struct gm20b_clk *clk, u32 dfs_det_cal) { … } static void gm20b_dvfs_program_dfs_detection(struct gm20b_clk *clk, struct gm20b_clk_dvfs *dvfs) { … } static int gm20b_clk_prog(struct nvkm_clk *base) { … } static struct nvkm_pstate gm20b_pstates[] = …; static void gm20b_clk_fini(struct nvkm_clk *base) { … } static int gm20b_clk_init_dvfs(struct gm20b_clk *clk) { … } /* Forward declaration to detect speedo >=1 in gm20b_clk_init() */ static const struct nvkm_clk_func gm20b_clk; static int gm20b_clk_init(struct nvkm_clk *base) { … } static const struct nvkm_clk_func gm20b_clk_speedo0 = …; static const struct nvkm_clk_func gm20b_clk = …; static int gm20b_clk_new_speedo0(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_clk **pclk) { … } /* FUSE register */ #define FUSE_RESERVED_CALIB0 … #define FUSE_RESERVED_CALIB0_INTERCEPT_FRAC_SHIFT … #define FUSE_RESERVED_CALIB0_INTERCEPT_FRAC_WIDTH … #define FUSE_RESERVED_CALIB0_INTERCEPT_INT_SHIFT … #define FUSE_RESERVED_CALIB0_INTERCEPT_INT_WIDTH … #define FUSE_RESERVED_CALIB0_SLOPE_FRAC_SHIFT … #define FUSE_RESERVED_CALIB0_SLOPE_FRAC_WIDTH … #define FUSE_RESERVED_CALIB0_SLOPE_INT_SHIFT … #define FUSE_RESERVED_CALIB0_SLOPE_INT_WIDTH … #define FUSE_RESERVED_CALIB0_FUSE_REV_SHIFT … #define FUSE_RESERVED_CALIB0_FUSE_REV_WIDTH … static int gm20b_clk_init_fused_params(struct gm20b_clk *clk) { … } static int gm20b_clk_init_safe_fmax(struct gm20b_clk *clk) { … } int gm20b_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_clk **pclk) { … }
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