#include "priv.h"
#include <core/memory.h>
#include <subdev/acr.h>
#include <nvfw/flcn.h>
#include <nvfw/pmu.h>
static int
gm20b_pmu_acr_bootstrap_falcon_cb(void *priv, struct nvfw_falcon_msg *hdr)
{ … }
int
gm20b_pmu_acr_bootstrap_falcon(struct nvkm_falcon *falcon,
enum nvkm_acr_lsf_id id)
{ … }
void
gm20b_pmu_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
{ … }
void
gm20b_pmu_acr_bld_write(struct nvkm_acr *acr, u32 bld,
struct nvkm_acr_lsfw *lsfw)
{ … }
static const struct nvkm_acr_lsf_func
gm20b_pmu_acr = …;
static int
gm20b_pmu_acr_init_wpr_callback(void *priv, struct nvfw_falcon_msg *hdr)
{ … }
static int
gm20b_pmu_acr_init_wpr(struct nvkm_pmu *pmu)
{ … }
static int
gm20b_pmu_initmsg(struct nvkm_pmu *pmu)
{ … }
static void
gm20b_pmu_recv(struct nvkm_pmu *pmu)
{ … }
static void
gm20b_pmu_fini(struct nvkm_pmu *pmu)
{ … }
static int
gm20b_pmu_init(struct nvkm_pmu *pmu)
{ … }
const struct nvkm_pmu_func
gm20b_pmu = …;
#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
MODULE_FIRMWARE("nvidia/gm20b/pmu/desc.bin");
MODULE_FIRMWARE("nvidia/gm20b/pmu/image.bin");
MODULE_FIRMWARE("nvidia/gm20b/pmu/sig.bin");
#endif
int
gm20b_pmu_load(struct nvkm_pmu *pmu, int ver, const struct nvkm_pmu_fwif *fwif)
{ … }
static const struct nvkm_pmu_fwif
gm20b_pmu_fwif[] = …;
int
gm20b_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_pmu **ppmu)
{ … }