/* SPDX-License-Identifier: MIT */ #ifndef __NVKM_DISP_DP_H__ #define __NVKM_DISP_DP_H__ #include "outp.h" int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *, struct nvkm_outp **); void nvkm_dp_disable(struct nvkm_outp *, struct nvkm_ior *); void nvkm_dp_enable(struct nvkm_outp *, bool auxpwr); /* DPCD Receiver Capabilities */ #define DPCD_RC00_DPCD_REV … #define DPCD_RC01_MAX_LINK_RATE … #define DPCD_RC02 … #define DPCD_RC02_ENHANCED_FRAME_CAP … #define DPCD_RC02_TPS3_SUPPORTED … #define DPCD_RC02_MAX_LANE_COUNT … #define DPCD_RC03 … #define DPCD_RC03_TPS4_SUPPORTED … #define DPCD_RC03_MAX_DOWNSPREAD … #define DPCD_RC0E … #define DPCD_RC0E_AUX_RD_INTERVAL … #define DPCD_RC10_SUPPORTED_LINK_RATES(i) … #define DPCD_RC10_SUPPORTED_LINK_RATES__SIZE … /* DPCD Link Configuration */ #define DPCD_LC00_LINK_BW_SET … #define DPCD_LC01 … #define DPCD_LC01_ENHANCED_FRAME_EN … #define DPCD_LC01_LANE_COUNT_SET … #define DPCD_LC02 … #define DPCD_LC02_TRAINING_PATTERN_SET … #define DPCD_LC02_SCRAMBLING_DISABLE … #define DPCD_LC03(l) … #define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED … #define DPCD_LC03_PRE_EMPHASIS_SET … #define DPCD_LC03_MAX_SWING_REACHED … #define DPCD_LC03_VOLTAGE_SWING_SET … #define DPCD_LC0F … #define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED … #define DPCD_LC0F_LANE1_POST_CURSOR2_SET … #define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED … #define DPCD_LC0F_LANE0_POST_CURSOR2_SET … #define DPCD_LC10 … #define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED … #define DPCD_LC10_LANE3_POST_CURSOR2_SET … #define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED … #define DPCD_LC10_LANE2_POST_CURSOR2_SET … #define DPCD_LC15_LINK_RATE_SET … #define DPCD_LC15_LINK_RATE_SET_MASK … /* DPCD Link/Sink Status */ #define DPCD_LS02 … #define DPCD_LS02_LANE1_SYMBOL_LOCKED … #define DPCD_LS02_LANE1_CHANNEL_EQ_DONE … #define DPCD_LS02_LANE1_CR_DONE … #define DPCD_LS02_LANE0_SYMBOL_LOCKED … #define DPCD_LS02_LANE0_CHANNEL_EQ_DONE … #define DPCD_LS02_LANE0_CR_DONE … #define DPCD_LS03 … #define DPCD_LS03_LANE3_SYMBOL_LOCKED … #define DPCD_LS03_LANE3_CHANNEL_EQ_DONE … #define DPCD_LS03_LANE3_CR_DONE … #define DPCD_LS03_LANE2_SYMBOL_LOCKED … #define DPCD_LS03_LANE2_CHANNEL_EQ_DONE … #define DPCD_LS03_LANE2_CR_DONE … #define DPCD_LS04 … #define DPCD_LS04_LINK_STATUS_UPDATED … #define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED … #define DPCD_LS04_INTERLANE_ALIGN_DONE … #define DPCD_LS06 … #define DPCD_LS06_LANE1_PRE_EMPHASIS … #define DPCD_LS06_LANE1_VOLTAGE_SWING … #define DPCD_LS06_LANE0_PRE_EMPHASIS … #define DPCD_LS06_LANE0_VOLTAGE_SWING … #define DPCD_LS07 … #define DPCD_LS07_LANE3_PRE_EMPHASIS … #define DPCD_LS07_LANE3_VOLTAGE_SWING … #define DPCD_LS07_LANE2_PRE_EMPHASIS … #define DPCD_LS07_LANE2_VOLTAGE_SWING … #define DPCD_LS0C … #define DPCD_LS0C_LANE3_POST_CURSOR2 … #define DPCD_LS0C_LANE2_POST_CURSOR2 … #define DPCD_LS0C_LANE1_POST_CURSOR2 … #define DPCD_LS0C_LANE0_POST_CURSOR2 … /* DPCD Sink Control */ #define DPCD_SC00 … #define DPCD_SC00_SET_POWER … #define DPCD_SC00_SET_POWER_D0 … #define DPCD_SC00_SET_POWER_D3 … #define DPCD_LTTPR_REV … #define DPCD_LTTPR_MODE … #define DPCD_LTTPR_MODE_TRANSPARENT … #define DPCD_LTTPR_MODE_NON_TRANSPARENT … #define DPCD_LTTPR_PATTERN_SET(i) … #define DPCD_LTTPR_LANE0_SET(i) … #define DPCD_LTTPR_AUX_RD_INTERVAL(i) … #define DPCD_LTTPR_LANE0_1_STATUS(i) … #define DPCD_LTTPR_LANE0_1_ADJUST(i) … #endif
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