/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * TI Palmas * * Copyright 2011-2013 Texas Instruments Inc. * * Author: Graeme Gregory <[email protected]> * Author: Ian Lartey <[email protected]> */ #ifndef __LINUX_MFD_PALMAS_H #define __LINUX_MFD_PALMAS_H #include <linux/usb/otg.h> #include <linux/leds.h> #include <linux/regmap.h> #include <linux/regulator/driver.h> #include <linux/extcon-provider.h> #include <linux/usb/phy_companion.h> #define PALMAS_NUM_CLIENTS … /* The ID_REVISION NUMBERS */ #define PALMAS_CHIP_OLD_ID … #define PALMAS_CHIP_ID … #define PALMAS_CHIP_CHARGER_ID … #define TPS65917_RESERVED … #define is_palmas(a) … #define is_palmas_charger(a) … /** * Palmas PMIC feature types * * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST * regulator. * * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a * specific feature (above) or not. Return non-zero, if yes. */ #define PALMAS_PMIC_FEATURE_SMPS10_BOOST … #define PALMAS_PMIC_HAS(b, f) … struct palmas_pmic; struct palmas_gpadc; struct palmas_resource; struct palmas_usb; struct palmas_pmic_driver_data; struct palmas_pmic_platform_data; enum palmas_usb_state { … }; struct palmas { … }; #define PALMAS_EXT_REQ … struct palmas_sleep_requestor_info { … }; struct palmas_regs_info { … }; struct palmas_pmic_driver_data { … }; struct palmas_gpadc_platform_data { … }; struct palmas_reg_init { … }; enum palmas_regulators { … }; enum tps65917_regulators { … }; /* External controll signal name */ enum { … }; /* * Palmas device resources can be controlled externally for * enabling/disabling it rather than register write through i2c. * Add the external controlled requestor ID for different resources. */ enum palmas_external_requestor_id { … }; enum tps65917_external_requestor_id { … }; struct palmas_pmic_platform_data { … }; struct palmas_usb_platform_data { … }; struct palmas_resource_platform_data { … }; struct palmas_clk_platform_data { … }; struct palmas_platform_data { … }; struct palmas_gpadc_calibration { … }; #define PALMAS_DATASHEET_NAME(_name) … struct palmas_gpadc_result { … }; #define PALMAS_MAX_CHANNELS … /* Define the tps65917 IRQ numbers */ enum tps65917_irqs { … }; /* Define the palmas IRQ numbers */ enum palmas_irqs { … }; /* Palmas GPADC Channels */ enum { … }; /* Palmas GPADC Channel0 Current Source */ enum { … }; /* Palmas GPADC Channel3 Current Source */ enum { … }; struct palmas_pmic { … }; struct palmas_resource { … }; struct palmas_usb { … }; #define comparator_to_palmas(x) … enum usb_irq_events { … }; /* defines so we can store the mux settings */ #define PALMAS_GPIO_0_MUXED … #define PALMAS_GPIO_1_MUXED … #define PALMAS_GPIO_2_MUXED … #define PALMAS_GPIO_3_MUXED … #define PALMAS_GPIO_4_MUXED … #define PALMAS_GPIO_5_MUXED … #define PALMAS_GPIO_6_MUXED … #define PALMAS_GPIO_7_MUXED … #define PALMAS_LED1_MUXED … #define PALMAS_LED2_MUXED … #define PALMAS_PWM1_MUXED … #define PALMAS_PWM2_MUXED … /* helper macro to get correct slave number */ #define PALMAS_BASE_TO_SLAVE(x) … #define PALMAS_BASE_TO_REG(x, y) … /* Base addresses of IP blocks in Palmas */ #define PALMAS_SMPS_DVS_BASE … #define PALMAS_RTC_BASE … #define PALMAS_VALIDITY_BASE … #define PALMAS_SMPS_BASE … #define PALMAS_LDO_BASE … #define PALMAS_DVFS_BASE … #define PALMAS_PMU_CONTROL_BASE … #define PALMAS_RESOURCE_BASE … #define PALMAS_PU_PD_OD_BASE … #define PALMAS_LED_BASE … #define PALMAS_INTERRUPT_BASE … #define PALMAS_USB_OTG_BASE … #define PALMAS_VIBRATOR_BASE … #define PALMAS_GPIO_BASE … #define PALMAS_USB_BASE … #define PALMAS_GPADC_BASE … #define PALMAS_TRIM_GPADC_BASE … /* Registers for function RTC */ #define PALMAS_SECONDS_REG … #define PALMAS_MINUTES_REG … #define PALMAS_HOURS_REG … #define PALMAS_DAYS_REG … #define PALMAS_MONTHS_REG … #define PALMAS_YEARS_REG … #define PALMAS_WEEKS_REG … #define PALMAS_ALARM_SECONDS_REG … #define PALMAS_ALARM_MINUTES_REG … #define PALMAS_ALARM_HOURS_REG … #define PALMAS_ALARM_DAYS_REG … #define PALMAS_ALARM_MONTHS_REG … #define PALMAS_ALARM_YEARS_REG … #define PALMAS_RTC_CTRL_REG … #define PALMAS_RTC_STATUS_REG … #define PALMAS_RTC_INTERRUPTS_REG … #define PALMAS_RTC_COMP_LSB_REG … #define PALMAS_RTC_COMP_MSB_REG … #define PALMAS_RTC_RES_PROG_REG … #define PALMAS_RTC_RESET_STATUS_REG … /* Bit definitions for SECONDS_REG */ #define PALMAS_SECONDS_REG_SEC1_MASK … #define PALMAS_SECONDS_REG_SEC1_SHIFT … #define PALMAS_SECONDS_REG_SEC0_MASK … #define PALMAS_SECONDS_REG_SEC0_SHIFT … /* Bit definitions for MINUTES_REG */ #define PALMAS_MINUTES_REG_MIN1_MASK … #define PALMAS_MINUTES_REG_MIN1_SHIFT … #define PALMAS_MINUTES_REG_MIN0_MASK … #define PALMAS_MINUTES_REG_MIN0_SHIFT … /* Bit definitions for HOURS_REG */ #define PALMAS_HOURS_REG_PM_NAM … #define PALMAS_HOURS_REG_PM_NAM_SHIFT … #define PALMAS_HOURS_REG_HOUR1_MASK … #define PALMAS_HOURS_REG_HOUR1_SHIFT … #define PALMAS_HOURS_REG_HOUR0_MASK … #define PALMAS_HOURS_REG_HOUR0_SHIFT … /* Bit definitions for DAYS_REG */ #define PALMAS_DAYS_REG_DAY1_MASK … #define PALMAS_DAYS_REG_DAY1_SHIFT … #define PALMAS_DAYS_REG_DAY0_MASK … #define PALMAS_DAYS_REG_DAY0_SHIFT … /* Bit definitions for MONTHS_REG */ #define PALMAS_MONTHS_REG_MONTH1 … #define PALMAS_MONTHS_REG_MONTH1_SHIFT … #define PALMAS_MONTHS_REG_MONTH0_MASK … #define PALMAS_MONTHS_REG_MONTH0_SHIFT … /* Bit definitions for YEARS_REG */ #define PALMAS_YEARS_REG_YEAR1_MASK … #define PALMAS_YEARS_REG_YEAR1_SHIFT … #define PALMAS_YEARS_REG_YEAR0_MASK … #define PALMAS_YEARS_REG_YEAR0_SHIFT … /* Bit definitions for WEEKS_REG */ #define PALMAS_WEEKS_REG_WEEK_MASK … #define PALMAS_WEEKS_REG_WEEK_SHIFT … /* Bit definitions for ALARM_SECONDS_REG */ #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK … #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT … #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK … #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT … /* Bit definitions for ALARM_MINUTES_REG */ #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK … #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT … #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK … #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT … /* Bit definitions for ALARM_HOURS_REG */ #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM … #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT … #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK … #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT … #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK … #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT … /* Bit definitions for ALARM_DAYS_REG */ #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK … #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT … #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK … #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT … /* Bit definitions for ALARM_MONTHS_REG */ #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 … #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT … #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK … #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT … /* Bit definitions for ALARM_YEARS_REG */ #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK … #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT … #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK … #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT … /* Bit definitions for RTC_CTRL_REG */ #define PALMAS_RTC_CTRL_REG_RTC_V_OPT … #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT … #define PALMAS_RTC_CTRL_REG_GET_TIME … #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT … #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER … #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT … #define PALMAS_RTC_CTRL_REG_TEST_MODE … #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT … #define PALMAS_RTC_CTRL_REG_MODE_12_24 … #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT … #define PALMAS_RTC_CTRL_REG_AUTO_COMP … #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT … #define PALMAS_RTC_CTRL_REG_ROUND_30S … #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT … #define PALMAS_RTC_CTRL_REG_STOP_RTC … #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT … /* Bit definitions for RTC_STATUS_REG */ #define PALMAS_RTC_STATUS_REG_POWER_UP … #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT … #define PALMAS_RTC_STATUS_REG_ALARM … #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT … #define PALMAS_RTC_STATUS_REG_EVENT_1D … #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT … #define PALMAS_RTC_STATUS_REG_EVENT_1H … #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT … #define PALMAS_RTC_STATUS_REG_EVENT_1M … #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT … #define PALMAS_RTC_STATUS_REG_EVENT_1S … #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT … #define PALMAS_RTC_STATUS_REG_RUN … #define PALMAS_RTC_STATUS_REG_RUN_SHIFT … /* Bit definitions for RTC_INTERRUPTS_REG */ #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN … #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT … #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM … #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT … #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER … #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT … #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK … #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT … /* Bit definitions for RTC_COMP_LSB_REG */ #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK … #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT … /* Bit definitions for RTC_COMP_MSB_REG */ #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK … #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT … /* Bit definitions for RTC_RES_PROG_REG */ #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK … #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT … /* Bit definitions for RTC_RESET_STATUS_REG */ #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS … #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT … /* Registers for function BACKUP */ #define PALMAS_BACKUP0 … #define PALMAS_BACKUP1 … #define PALMAS_BACKUP2 … #define PALMAS_BACKUP3 … #define PALMAS_BACKUP4 … #define PALMAS_BACKUP5 … #define PALMAS_BACKUP6 … #define PALMAS_BACKUP7 … /* Bit definitions for BACKUP0 */ #define PALMAS_BACKUP0_BACKUP_MASK … #define PALMAS_BACKUP0_BACKUP_SHIFT … /* Bit definitions for BACKUP1 */ #define PALMAS_BACKUP1_BACKUP_MASK … #define PALMAS_BACKUP1_BACKUP_SHIFT … /* Bit definitions for BACKUP2 */ #define PALMAS_BACKUP2_BACKUP_MASK … #define PALMAS_BACKUP2_BACKUP_SHIFT … /* Bit definitions for BACKUP3 */ #define PALMAS_BACKUP3_BACKUP_MASK … #define PALMAS_BACKUP3_BACKUP_SHIFT … /* Bit definitions for BACKUP4 */ #define PALMAS_BACKUP4_BACKUP_MASK … #define PALMAS_BACKUP4_BACKUP_SHIFT … /* Bit definitions for BACKUP5 */ #define PALMAS_BACKUP5_BACKUP_MASK … #define PALMAS_BACKUP5_BACKUP_SHIFT … /* Bit definitions for BACKUP6 */ #define PALMAS_BACKUP6_BACKUP_MASK … #define PALMAS_BACKUP6_BACKUP_SHIFT … /* Bit definitions for BACKUP7 */ #define PALMAS_BACKUP7_BACKUP_MASK … #define PALMAS_BACKUP7_BACKUP_SHIFT … /* Registers for function SMPS */ #define PALMAS_SMPS12_CTRL … #define PALMAS_SMPS12_TSTEP … #define PALMAS_SMPS12_FORCE … #define PALMAS_SMPS12_VOLTAGE … #define PALMAS_SMPS3_CTRL … #define PALMAS_SMPS3_VOLTAGE … #define PALMAS_SMPS45_CTRL … #define PALMAS_SMPS45_TSTEP … #define PALMAS_SMPS45_FORCE … #define PALMAS_SMPS45_VOLTAGE … #define PALMAS_SMPS6_CTRL … #define PALMAS_SMPS6_TSTEP … #define PALMAS_SMPS6_FORCE … #define PALMAS_SMPS6_VOLTAGE … #define PALMAS_SMPS7_CTRL … #define PALMAS_SMPS7_VOLTAGE … #define PALMAS_SMPS8_CTRL … #define PALMAS_SMPS8_TSTEP … #define PALMAS_SMPS8_FORCE … #define PALMAS_SMPS8_VOLTAGE … #define PALMAS_SMPS9_CTRL … #define PALMAS_SMPS9_VOLTAGE … #define PALMAS_SMPS10_CTRL … #define PALMAS_SMPS10_STATUS … #define PALMAS_SMPS_CTRL … #define PALMAS_SMPS_PD_CTRL … #define PALMAS_SMPS_DITHER_EN … #define PALMAS_SMPS_THERMAL_EN … #define PALMAS_SMPS_THERMAL_STATUS … #define PALMAS_SMPS_SHORT_STATUS … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN … #define PALMAS_SMPS_POWERGOOD_MASK1 … #define PALMAS_SMPS_POWERGOOD_MASK2 … /* Bit definitions for SMPS12_CTRL */ #define PALMAS_SMPS12_CTRL_WR_S … #define PALMAS_SMPS12_CTRL_WR_S_SHIFT … #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN … #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT … #define PALMAS_SMPS12_CTRL_STATUS_MASK … #define PALMAS_SMPS12_CTRL_STATUS_SHIFT … #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK … #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK … #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SMPS12_TSTEP */ #define PALMAS_SMPS12_TSTEP_TSTEP_MASK … #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT … /* Bit definitions for SMPS12_FORCE */ #define PALMAS_SMPS12_FORCE_CMD … #define PALMAS_SMPS12_FORCE_CMD_SHIFT … #define PALMAS_SMPS12_FORCE_VSEL_MASK … #define PALMAS_SMPS12_FORCE_VSEL_SHIFT … /* Bit definitions for SMPS12_VOLTAGE */ #define PALMAS_SMPS12_VOLTAGE_RANGE … #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT … #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK … #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT … /* Bit definitions for SMPS3_CTRL */ #define PALMAS_SMPS3_CTRL_WR_S … #define PALMAS_SMPS3_CTRL_WR_S_SHIFT … #define PALMAS_SMPS3_CTRL_STATUS_MASK … #define PALMAS_SMPS3_CTRL_STATUS_SHIFT … #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK … #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK … #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SMPS3_VOLTAGE */ #define PALMAS_SMPS3_VOLTAGE_RANGE … #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT … #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK … #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT … /* Bit definitions for SMPS45_CTRL */ #define PALMAS_SMPS45_CTRL_WR_S … #define PALMAS_SMPS45_CTRL_WR_S_SHIFT … #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN … #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT … #define PALMAS_SMPS45_CTRL_STATUS_MASK … #define PALMAS_SMPS45_CTRL_STATUS_SHIFT … #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK … #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK … #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SMPS45_TSTEP */ #define PALMAS_SMPS45_TSTEP_TSTEP_MASK … #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT … /* Bit definitions for SMPS45_FORCE */ #define PALMAS_SMPS45_FORCE_CMD … #define PALMAS_SMPS45_FORCE_CMD_SHIFT … #define PALMAS_SMPS45_FORCE_VSEL_MASK … #define PALMAS_SMPS45_FORCE_VSEL_SHIFT … /* Bit definitions for SMPS45_VOLTAGE */ #define PALMAS_SMPS45_VOLTAGE_RANGE … #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT … #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK … #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT … /* Bit definitions for SMPS6_CTRL */ #define PALMAS_SMPS6_CTRL_WR_S … #define PALMAS_SMPS6_CTRL_WR_S_SHIFT … #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN … #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT … #define PALMAS_SMPS6_CTRL_STATUS_MASK … #define PALMAS_SMPS6_CTRL_STATUS_SHIFT … #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK … #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK … #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SMPS6_TSTEP */ #define PALMAS_SMPS6_TSTEP_TSTEP_MASK … #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT … /* Bit definitions for SMPS6_FORCE */ #define PALMAS_SMPS6_FORCE_CMD … #define PALMAS_SMPS6_FORCE_CMD_SHIFT … #define PALMAS_SMPS6_FORCE_VSEL_MASK … #define PALMAS_SMPS6_FORCE_VSEL_SHIFT … /* Bit definitions for SMPS6_VOLTAGE */ #define PALMAS_SMPS6_VOLTAGE_RANGE … #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT … #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK … #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT … /* Bit definitions for SMPS7_CTRL */ #define PALMAS_SMPS7_CTRL_WR_S … #define PALMAS_SMPS7_CTRL_WR_S_SHIFT … #define PALMAS_SMPS7_CTRL_STATUS_MASK … #define PALMAS_SMPS7_CTRL_STATUS_SHIFT … #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK … #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK … #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SMPS7_VOLTAGE */ #define PALMAS_SMPS7_VOLTAGE_RANGE … #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT … #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK … #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT … /* Bit definitions for SMPS8_CTRL */ #define PALMAS_SMPS8_CTRL_WR_S … #define PALMAS_SMPS8_CTRL_WR_S_SHIFT … #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN … #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT … #define PALMAS_SMPS8_CTRL_STATUS_MASK … #define PALMAS_SMPS8_CTRL_STATUS_SHIFT … #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK … #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK … #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SMPS8_TSTEP */ #define PALMAS_SMPS8_TSTEP_TSTEP_MASK … #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT … /* Bit definitions for SMPS8_FORCE */ #define PALMAS_SMPS8_FORCE_CMD … #define PALMAS_SMPS8_FORCE_CMD_SHIFT … #define PALMAS_SMPS8_FORCE_VSEL_MASK … #define PALMAS_SMPS8_FORCE_VSEL_SHIFT … /* Bit definitions for SMPS8_VOLTAGE */ #define PALMAS_SMPS8_VOLTAGE_RANGE … #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT … #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK … #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT … /* Bit definitions for SMPS9_CTRL */ #define PALMAS_SMPS9_CTRL_WR_S … #define PALMAS_SMPS9_CTRL_WR_S_SHIFT … #define PALMAS_SMPS9_CTRL_STATUS_MASK … #define PALMAS_SMPS9_CTRL_STATUS_SHIFT … #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK … #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK … #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SMPS9_VOLTAGE */ #define PALMAS_SMPS9_VOLTAGE_RANGE … #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT … #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK … #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT … /* Bit definitions for SMPS10_CTRL */ #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK … #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK … #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SMPS10_STATUS */ #define PALMAS_SMPS10_STATUS_STATUS_MASK … #define PALMAS_SMPS10_STATUS_STATUS_SHIFT … /* Bit definitions for SMPS_CTRL */ #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN … #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT … #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN … #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT … #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK … #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT … #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK … #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT … /* Bit definitions for SMPS_PD_CTRL */ #define PALMAS_SMPS_PD_CTRL_SMPS9 … #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT … #define PALMAS_SMPS_PD_CTRL_SMPS8 … #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT … #define PALMAS_SMPS_PD_CTRL_SMPS7 … #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT … #define PALMAS_SMPS_PD_CTRL_SMPS6 … #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT … #define PALMAS_SMPS_PD_CTRL_SMPS45 … #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT … #define PALMAS_SMPS_PD_CTRL_SMPS3 … #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT … #define PALMAS_SMPS_PD_CTRL_SMPS12 … #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT … /* Bit definitions for SMPS_THERMAL_EN */ #define PALMAS_SMPS_THERMAL_EN_SMPS9 … #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT … #define PALMAS_SMPS_THERMAL_EN_SMPS8 … #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT … #define PALMAS_SMPS_THERMAL_EN_SMPS6 … #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT … #define PALMAS_SMPS_THERMAL_EN_SMPS457 … #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT … #define PALMAS_SMPS_THERMAL_EN_SMPS123 … #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT … /* Bit definitions for SMPS_THERMAL_STATUS */ #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 … #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT … #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 … #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT … #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 … #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT … #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 … #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT … #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 … #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT … /* Bit definitions for SMPS_SHORT_STATUS */ #define PALMAS_SMPS_SHORT_STATUS_SMPS10 … #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT … #define PALMAS_SMPS_SHORT_STATUS_SMPS9 … #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT … #define PALMAS_SMPS_SHORT_STATUS_SMPS8 … #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT … #define PALMAS_SMPS_SHORT_STATUS_SMPS7 … #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT … #define PALMAS_SMPS_SHORT_STATUS_SMPS6 … #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT … #define PALMAS_SMPS_SHORT_STATUS_SMPS45 … #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT … #define PALMAS_SMPS_SHORT_STATUS_SMPS3 … #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT … #define PALMAS_SMPS_SHORT_STATUS_SMPS12 … #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT … /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 … #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT … /* Bit definitions for SMPS_POWERGOOD_MASK1 */ #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 … #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT … /* Bit definitions for SMPS_POWERGOOD_MASK2 */ #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT … #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT … #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 … #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT … #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS … #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT … #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK … #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT … /* Registers for function LDO */ #define PALMAS_LDO1_CTRL … #define PALMAS_LDO1_VOLTAGE … #define PALMAS_LDO2_CTRL … #define PALMAS_LDO2_VOLTAGE … #define PALMAS_LDO3_CTRL … #define PALMAS_LDO3_VOLTAGE … #define PALMAS_LDO4_CTRL … #define PALMAS_LDO4_VOLTAGE … #define PALMAS_LDO5_CTRL … #define PALMAS_LDO5_VOLTAGE … #define PALMAS_LDO6_CTRL … #define PALMAS_LDO6_VOLTAGE … #define PALMAS_LDO7_CTRL … #define PALMAS_LDO7_VOLTAGE … #define PALMAS_LDO8_CTRL … #define PALMAS_LDO8_VOLTAGE … #define PALMAS_LDO9_CTRL … #define PALMAS_LDO9_VOLTAGE … #define PALMAS_LDOLN_CTRL … #define PALMAS_LDOLN_VOLTAGE … #define PALMAS_LDOUSB_CTRL … #define PALMAS_LDOUSB_VOLTAGE … #define PALMAS_LDO_CTRL … #define PALMAS_LDO_PD_CTRL1 … #define PALMAS_LDO_PD_CTRL2 … #define PALMAS_LDO_SHORT_STATUS1 … #define PALMAS_LDO_SHORT_STATUS2 … /* Bit definitions for LDO1_CTRL */ #define PALMAS_LDO1_CTRL_WR_S … #define PALMAS_LDO1_CTRL_WR_S_SHIFT … #define PALMAS_LDO1_CTRL_STATUS … #define PALMAS_LDO1_CTRL_STATUS_SHIFT … #define PALMAS_LDO1_CTRL_MODE_SLEEP … #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_LDO1_CTRL_MODE_ACTIVE … #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO1_VOLTAGE */ #define PALMAS_LDO1_VOLTAGE_VSEL_MASK … #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO2_CTRL */ #define PALMAS_LDO2_CTRL_WR_S … #define PALMAS_LDO2_CTRL_WR_S_SHIFT … #define PALMAS_LDO2_CTRL_STATUS … #define PALMAS_LDO2_CTRL_STATUS_SHIFT … #define PALMAS_LDO2_CTRL_MODE_SLEEP … #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_LDO2_CTRL_MODE_ACTIVE … #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO2_VOLTAGE */ #define PALMAS_LDO2_VOLTAGE_VSEL_MASK … #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO3_CTRL */ #define PALMAS_LDO3_CTRL_WR_S … #define PALMAS_LDO3_CTRL_WR_S_SHIFT … #define PALMAS_LDO3_CTRL_STATUS … #define PALMAS_LDO3_CTRL_STATUS_SHIFT … #define PALMAS_LDO3_CTRL_MODE_SLEEP … #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_LDO3_CTRL_MODE_ACTIVE … #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO3_VOLTAGE */ #define PALMAS_LDO3_VOLTAGE_VSEL_MASK … #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO4_CTRL */ #define PALMAS_LDO4_CTRL_WR_S … #define PALMAS_LDO4_CTRL_WR_S_SHIFT … #define PALMAS_LDO4_CTRL_STATUS … #define PALMAS_LDO4_CTRL_STATUS_SHIFT … #define PALMAS_LDO4_CTRL_MODE_SLEEP … #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_LDO4_CTRL_MODE_ACTIVE … #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO4_VOLTAGE */ #define PALMAS_LDO4_VOLTAGE_VSEL_MASK … #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO5_CTRL */ #define PALMAS_LDO5_CTRL_WR_S … #define PALMAS_LDO5_CTRL_WR_S_SHIFT … #define PALMAS_LDO5_CTRL_STATUS … #define PALMAS_LDO5_CTRL_STATUS_SHIFT … #define PALMAS_LDO5_CTRL_MODE_SLEEP … #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_LDO5_CTRL_MODE_ACTIVE … #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO5_VOLTAGE */ #define PALMAS_LDO5_VOLTAGE_VSEL_MASK … #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO6_CTRL */ #define PALMAS_LDO6_CTRL_WR_S … #define PALMAS_LDO6_CTRL_WR_S_SHIFT … #define PALMAS_LDO6_CTRL_LDO_VIB_EN … #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT … #define PALMAS_LDO6_CTRL_STATUS … #define PALMAS_LDO6_CTRL_STATUS_SHIFT … #define PALMAS_LDO6_CTRL_MODE_SLEEP … #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_LDO6_CTRL_MODE_ACTIVE … #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO6_VOLTAGE */ #define PALMAS_LDO6_VOLTAGE_VSEL_MASK … #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO7_CTRL */ #define PALMAS_LDO7_CTRL_WR_S … #define PALMAS_LDO7_CTRL_WR_S_SHIFT … #define PALMAS_LDO7_CTRL_STATUS … #define PALMAS_LDO7_CTRL_STATUS_SHIFT … #define PALMAS_LDO7_CTRL_MODE_SLEEP … #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_LDO7_CTRL_MODE_ACTIVE … #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO7_VOLTAGE */ #define PALMAS_LDO7_VOLTAGE_VSEL_MASK … #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO8_CTRL */ #define PALMAS_LDO8_CTRL_WR_S … #define PALMAS_LDO8_CTRL_WR_S_SHIFT … #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN … #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT … #define PALMAS_LDO8_CTRL_STATUS … #define PALMAS_LDO8_CTRL_STATUS_SHIFT … #define PALMAS_LDO8_CTRL_MODE_SLEEP … #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_LDO8_CTRL_MODE_ACTIVE … #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO8_VOLTAGE */ #define PALMAS_LDO8_VOLTAGE_VSEL_MASK … #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO9_CTRL */ #define PALMAS_LDO9_CTRL_WR_S … #define PALMAS_LDO9_CTRL_WR_S_SHIFT … #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN … #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT … #define PALMAS_LDO9_CTRL_STATUS … #define PALMAS_LDO9_CTRL_STATUS_SHIFT … #define PALMAS_LDO9_CTRL_MODE_SLEEP … #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_LDO9_CTRL_MODE_ACTIVE … #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO9_VOLTAGE */ #define PALMAS_LDO9_VOLTAGE_VSEL_MASK … #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDOLN_CTRL */ #define PALMAS_LDOLN_CTRL_WR_S … #define PALMAS_LDOLN_CTRL_WR_S_SHIFT … #define PALMAS_LDOLN_CTRL_STATUS … #define PALMAS_LDOLN_CTRL_STATUS_SHIFT … #define PALMAS_LDOLN_CTRL_MODE_SLEEP … #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_LDOLN_CTRL_MODE_ACTIVE … #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDOLN_VOLTAGE */ #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK … #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDOUSB_CTRL */ #define PALMAS_LDOUSB_CTRL_WR_S … #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT … #define PALMAS_LDOUSB_CTRL_STATUS … #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT … #define PALMAS_LDOUSB_CTRL_MODE_SLEEP … #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE … #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDOUSB_VOLTAGE */ #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK … #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO_CTRL */ #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS … #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT … /* Bit definitions for LDO_PD_CTRL1 */ #define PALMAS_LDO_PD_CTRL1_LDO8 … #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT … #define PALMAS_LDO_PD_CTRL1_LDO7 … #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT … #define PALMAS_LDO_PD_CTRL1_LDO6 … #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT … #define PALMAS_LDO_PD_CTRL1_LDO5 … #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT … #define PALMAS_LDO_PD_CTRL1_LDO4 … #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT … #define PALMAS_LDO_PD_CTRL1_LDO3 … #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT … #define PALMAS_LDO_PD_CTRL1_LDO2 … #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT … #define PALMAS_LDO_PD_CTRL1_LDO1 … #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT … /* Bit definitions for LDO_PD_CTRL2 */ #define PALMAS_LDO_PD_CTRL2_LDOUSB … #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT … #define PALMAS_LDO_PD_CTRL2_LDOLN … #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT … #define PALMAS_LDO_PD_CTRL2_LDO9 … #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT … /* Bit definitions for LDO_SHORT_STATUS1 */ #define PALMAS_LDO_SHORT_STATUS1_LDO8 … #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT … #define PALMAS_LDO_SHORT_STATUS1_LDO7 … #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT … #define PALMAS_LDO_SHORT_STATUS1_LDO6 … #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT … #define PALMAS_LDO_SHORT_STATUS1_LDO5 … #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT … #define PALMAS_LDO_SHORT_STATUS1_LDO4 … #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT … #define PALMAS_LDO_SHORT_STATUS1_LDO3 … #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT … #define PALMAS_LDO_SHORT_STATUS1_LDO2 … #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT … #define PALMAS_LDO_SHORT_STATUS1_LDO1 … #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT … /* Bit definitions for LDO_SHORT_STATUS2 */ #define PALMAS_LDO_SHORT_STATUS2_LDOVANA … #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT … #define PALMAS_LDO_SHORT_STATUS2_LDOUSB … #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT … #define PALMAS_LDO_SHORT_STATUS2_LDOLN … #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT … #define PALMAS_LDO_SHORT_STATUS2_LDO9 … #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT … /* Registers for function PMU_CONTROL */ #define PALMAS_DEV_CTRL … #define PALMAS_POWER_CTRL … #define PALMAS_VSYS_LO … #define PALMAS_VSYS_MON … #define PALMAS_VBAT_MON … #define PALMAS_WATCHDOG … #define PALMAS_BOOT_STATUS … #define PALMAS_BATTERY_BOUNCE … #define PALMAS_BACKUP_BATTERY_CTRL … #define PALMAS_LONG_PRESS_KEY … #define PALMAS_OSC_THERM_CTRL … #define PALMAS_BATDEBOUNCING … #define PALMAS_SWOFF_HWRST … #define PALMAS_SWOFF_COLDRST … #define PALMAS_SWOFF_STATUS … #define PALMAS_PMU_CONFIG … #define PALMAS_SPARE … #define PALMAS_PMU_SECONDARY_INT … #define PALMAS_SW_REVISION … #define PALMAS_EXT_CHRG_CTRL … #define PALMAS_PMU_SECONDARY_INT2 … /* Bit definitions for DEV_CTRL */ #define PALMAS_DEV_CTRL_DEV_STATUS_MASK … #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT … #define PALMAS_DEV_CTRL_SW_RST … #define PALMAS_DEV_CTRL_SW_RST_SHIFT … #define PALMAS_DEV_CTRL_DEV_ON … #define PALMAS_DEV_CTRL_DEV_ON_SHIFT … /* Bit definitions for POWER_CTRL */ #define PALMAS_POWER_CTRL_ENABLE2_MASK … #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT … #define PALMAS_POWER_CTRL_ENABLE1_MASK … #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT … #define PALMAS_POWER_CTRL_NSLEEP_MASK … #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT … /* Bit definitions for VSYS_LO */ #define PALMAS_VSYS_LO_THRESHOLD_MASK … #define PALMAS_VSYS_LO_THRESHOLD_SHIFT … /* Bit definitions for VSYS_MON */ #define PALMAS_VSYS_MON_ENABLE … #define PALMAS_VSYS_MON_ENABLE_SHIFT … #define PALMAS_VSYS_MON_THRESHOLD_MASK … #define PALMAS_VSYS_MON_THRESHOLD_SHIFT … /* Bit definitions for VBAT_MON */ #define PALMAS_VBAT_MON_ENABLE … #define PALMAS_VBAT_MON_ENABLE_SHIFT … #define PALMAS_VBAT_MON_THRESHOLD_MASK … #define PALMAS_VBAT_MON_THRESHOLD_SHIFT … /* Bit definitions for WATCHDOG */ #define PALMAS_WATCHDOG_LOCK … #define PALMAS_WATCHDOG_LOCK_SHIFT … #define PALMAS_WATCHDOG_ENABLE … #define PALMAS_WATCHDOG_ENABLE_SHIFT … #define PALMAS_WATCHDOG_MODE … #define PALMAS_WATCHDOG_MODE_SHIFT … #define PALMAS_WATCHDOG_TIMER_MASK … #define PALMAS_WATCHDOG_TIMER_SHIFT … /* Bit definitions for BOOT_STATUS */ #define PALMAS_BOOT_STATUS_BOOT1 … #define PALMAS_BOOT_STATUS_BOOT1_SHIFT … #define PALMAS_BOOT_STATUS_BOOT0 … #define PALMAS_BOOT_STATUS_BOOT0_SHIFT … /* Bit definitions for BATTERY_BOUNCE */ #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK … #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT … /* Bit definitions for BACKUP_BATTERY_CTRL */ #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 … #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT … #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP … #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT … #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF … #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT … #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN … #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT … #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG … #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT … #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK … #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT … #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN … #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT … /* Bit definitions for LONG_PRESS_KEY */ #define PALMAS_LONG_PRESS_KEY_LPK_LOCK … #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT … #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR … #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT … #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK … #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT … #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK … #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT … /* Bit definitions for OSC_THERM_CTRL */ #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP … #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT … #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP … #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT … #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP … #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT … #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP … #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT … #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK … #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT … #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS … #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT … #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE … #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT … /* Bit definitions for BATDEBOUNCING */ #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS … #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT … #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK … #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT … #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK … #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT … /* Bit definitions for SWOFF_HWRST */ #define PALMAS_SWOFF_HWRST_PWRON_LPK … #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT … #define PALMAS_SWOFF_HWRST_PWRDOWN … #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT … #define PALMAS_SWOFF_HWRST_WTD … #define PALMAS_SWOFF_HWRST_WTD_SHIFT … #define PALMAS_SWOFF_HWRST_TSHUT … #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT … #define PALMAS_SWOFF_HWRST_RESET_IN … #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT … #define PALMAS_SWOFF_HWRST_SW_RST … #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT … #define PALMAS_SWOFF_HWRST_VSYS_LO … #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT … #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN … #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT … /* Bit definitions for SWOFF_COLDRST */ #define PALMAS_SWOFF_COLDRST_PWRON_LPK … #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT … #define PALMAS_SWOFF_COLDRST_PWRDOWN … #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT … #define PALMAS_SWOFF_COLDRST_WTD … #define PALMAS_SWOFF_COLDRST_WTD_SHIFT … #define PALMAS_SWOFF_COLDRST_TSHUT … #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT … #define PALMAS_SWOFF_COLDRST_RESET_IN … #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT … #define PALMAS_SWOFF_COLDRST_SW_RST … #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT … #define PALMAS_SWOFF_COLDRST_VSYS_LO … #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT … #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN … #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT … /* Bit definitions for SWOFF_STATUS */ #define PALMAS_SWOFF_STATUS_PWRON_LPK … #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT … #define PALMAS_SWOFF_STATUS_PWRDOWN … #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT … #define PALMAS_SWOFF_STATUS_WTD … #define PALMAS_SWOFF_STATUS_WTD_SHIFT … #define PALMAS_SWOFF_STATUS_TSHUT … #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT … #define PALMAS_SWOFF_STATUS_RESET_IN … #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT … #define PALMAS_SWOFF_STATUS_SW_RST … #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT … #define PALMAS_SWOFF_STATUS_VSYS_LO … #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT … #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN … #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT … /* Bit definitions for PMU_CONFIG */ #define PALMAS_PMU_CONFIG_MULTI_CELL_EN … #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT … #define PALMAS_PMU_CONFIG_SPARE_MASK … #define PALMAS_PMU_CONFIG_SPARE_SHIFT … #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK … #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT … #define PALMAS_PMU_CONFIG_GATE_RESET_OUT … #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT … #define PALMAS_PMU_CONFIG_AUTODEVON … #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT … /* Bit definitions for SPARE */ #define PALMAS_SPARE_SPARE_MASK … #define PALMAS_SPARE_SPARE_SHIFT … #define PALMAS_SPARE_REGEN3_OD … #define PALMAS_SPARE_REGEN3_OD_SHIFT … #define PALMAS_SPARE_REGEN2_OD … #define PALMAS_SPARE_REGEN2_OD_SHIFT … #define PALMAS_SPARE_REGEN1_OD … #define PALMAS_SPARE_REGEN1_OD_SHIFT … /* Bit definitions for PMU_SECONDARY_INT */ #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC … #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT … #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC … #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT … #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC … #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT … #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC … #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT … #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK … #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT … #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK … #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT … #define PALMAS_PMU_SECONDARY_INT_BB_MASK … #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT … #define PALMAS_PMU_SECONDARY_INT_FBI_MASK … #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT … /* Bit definitions for SW_REVISION */ #define PALMAS_SW_REVISION_SW_REVISION_MASK … #define PALMAS_SW_REVISION_SW_REVISION_SHIFT … /* Bit definitions for EXT_CHRG_CTRL */ #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS … #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT … #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS … #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT … #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY … #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT … #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N … #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT … #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN … #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT … #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN … #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT … /* Bit definitions for PMU_SECONDARY_INT2 */ #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC … #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT … #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC … #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT … #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK … #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT … #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK … #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT … /* Registers for function RESOURCE */ #define PALMAS_CLK32KG_CTRL … #define PALMAS_CLK32KGAUDIO_CTRL … #define PALMAS_REGEN1_CTRL … #define PALMAS_REGEN2_CTRL … #define PALMAS_SYSEN1_CTRL … #define PALMAS_SYSEN2_CTRL … #define PALMAS_NSLEEP_RES_ASSIGN … #define PALMAS_NSLEEP_SMPS_ASSIGN … #define PALMAS_NSLEEP_LDO_ASSIGN1 … #define PALMAS_NSLEEP_LDO_ASSIGN2 … #define PALMAS_ENABLE1_RES_ASSIGN … #define PALMAS_ENABLE1_SMPS_ASSIGN … #define PALMAS_ENABLE1_LDO_ASSIGN1 … #define PALMAS_ENABLE1_LDO_ASSIGN2 … #define PALMAS_ENABLE2_RES_ASSIGN … #define PALMAS_ENABLE2_SMPS_ASSIGN … #define PALMAS_ENABLE2_LDO_ASSIGN1 … #define PALMAS_ENABLE2_LDO_ASSIGN2 … #define PALMAS_REGEN3_CTRL … /* Bit definitions for CLK32KG_CTRL */ #define PALMAS_CLK32KG_CTRL_STATUS … #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT … #define PALMAS_CLK32KG_CTRL_MODE_SLEEP … #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE … #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for CLK32KGAUDIO_CTRL */ #define PALMAS_CLK32KGAUDIO_CTRL_STATUS … #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT … #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 … #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT … #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP … #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE … #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for REGEN1_CTRL */ #define PALMAS_REGEN1_CTRL_STATUS … #define PALMAS_REGEN1_CTRL_STATUS_SHIFT … #define PALMAS_REGEN1_CTRL_MODE_SLEEP … #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_REGEN1_CTRL_MODE_ACTIVE … #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for REGEN2_CTRL */ #define PALMAS_REGEN2_CTRL_STATUS … #define PALMAS_REGEN2_CTRL_STATUS_SHIFT … #define PALMAS_REGEN2_CTRL_MODE_SLEEP … #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_REGEN2_CTRL_MODE_ACTIVE … #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SYSEN1_CTRL */ #define PALMAS_SYSEN1_CTRL_STATUS … #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT … #define PALMAS_SYSEN1_CTRL_MODE_SLEEP … #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE … #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SYSEN2_CTRL */ #define PALMAS_SYSEN2_CTRL_STATUS … #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT … #define PALMAS_SYSEN2_CTRL_MODE_SLEEP … #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE … #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for NSLEEP_RES_ASSIGN */ #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 … #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT … #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO … #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT … #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG … #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT … #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 … #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT … #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 … #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT … #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 … #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT … #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 … #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT … /* Bit definitions for NSLEEP_SMPS_ASSIGN */ #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 … #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT … /* Bit definitions for NSLEEP_LDO_ASSIGN1 */ #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 … #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT … /* Bit definitions for NSLEEP_LDO_ASSIGN2 */ #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB … #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT … #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN … #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT … #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 … #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT … /* Bit definitions for ENABLE1_RES_ASSIGN */ #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 … #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT … #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO … #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT … #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG … #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT … #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 … #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT … #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 … #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT … #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 … #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT … #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 … #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT … /* Bit definitions for ENABLE1_SMPS_ASSIGN */ #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 … #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT … /* Bit definitions for ENABLE1_LDO_ASSIGN1 */ #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 … #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT … /* Bit definitions for ENABLE1_LDO_ASSIGN2 */ #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB … #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT … #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN … #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT … #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 … #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT … /* Bit definitions for ENABLE2_RES_ASSIGN */ #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 … #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT … #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO … #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT … #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG … #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT … #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 … #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT … #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 … #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT … #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 … #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT … #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 … #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT … /* Bit definitions for ENABLE2_SMPS_ASSIGN */ #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 … #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT … /* Bit definitions for ENABLE2_LDO_ASSIGN1 */ #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 … #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT … /* Bit definitions for ENABLE2_LDO_ASSIGN2 */ #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB … #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT … #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN … #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT … #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 … #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT … /* Bit definitions for REGEN3_CTRL */ #define PALMAS_REGEN3_CTRL_STATUS … #define PALMAS_REGEN3_CTRL_STATUS_SHIFT … #define PALMAS_REGEN3_CTRL_MODE_SLEEP … #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT … #define PALMAS_REGEN3_CTRL_MODE_ACTIVE … #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT … /* Registers for function PAD_CONTROL */ #define PALMAS_OD_OUTPUT_CTRL2 … #define PALMAS_POLARITY_CTRL2 … #define PALMAS_PU_PD_INPUT_CTRL1 … #define PALMAS_PU_PD_INPUT_CTRL2 … #define PALMAS_PU_PD_INPUT_CTRL3 … #define PALMAS_PU_PD_INPUT_CTRL5 … #define PALMAS_OD_OUTPUT_CTRL … #define PALMAS_POLARITY_CTRL … #define PALMAS_PRIMARY_SECONDARY_PAD1 … #define PALMAS_PRIMARY_SECONDARY_PAD2 … #define PALMAS_I2C_SPI … #define PALMAS_PU_PD_INPUT_CTRL4 … #define PALMAS_PRIMARY_SECONDARY_PAD3 … #define PALMAS_PRIMARY_SECONDARY_PAD4 … /* Bit definitions for PU_PD_INPUT_CTRL1 */ #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD … #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU … #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD … #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD … #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU … #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT … /* Bit definitions for PU_PD_INPUT_CTRL2 */ #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU … #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD … #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU … #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD … #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU … #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD … #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT … /* Bit definitions for PU_PD_INPUT_CTRL3 */ #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD … #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD … #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD … #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD … #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT … /* Bit definitions for OD_OUTPUT_CTRL */ #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD … #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT … #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD … #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT … #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD … #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT … #define PALMAS_OD_OUTPUT_CTRL_INT_OD … #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT … /* Bit definitions for POLARITY_CTRL */ #define PALMAS_POLARITY_CTRL_INT_POLARITY … #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT … #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY … #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT … #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY … #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT … #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY … #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT … #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY … #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT … #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY … #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT … #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY … #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT … #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY … #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT … /* Bit definitions for PRIMARY_SECONDARY_PAD1 */ #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 … #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT … #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK … #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT … #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK … #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT … #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 … #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT … #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC … #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT … #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD … #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT … /* Bit definitions for PRIMARY_SECONDARY_PAD2 */ #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK … #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT … #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 … #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT … #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK … #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT … #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 … #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT … /* Bit definitions for I2C_SPI */ #define PALMAS_I2C_SPI_I2C2OTP_EN … #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT … #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL … #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT … #define PALMAS_I2C_SPI_ID_I2C2 … #define PALMAS_I2C_SPI_ID_I2C2_SHIFT … #define PALMAS_I2C_SPI_I2C_SPI … #define PALMAS_I2C_SPI_I2C_SPI_SHIFT … #define PALMAS_I2C_SPI_ID_I2C1_MASK … #define PALMAS_I2C_SPI_ID_I2C1_SHIFT … /* Bit definitions for PU_PD_INPUT_CTRL4 */ #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD … #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD … #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD … #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT … #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD … #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT … /* Bit definitions for PRIMARY_SECONDARY_PAD3 */ #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 … #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT … #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 … #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT … /* Registers for function LED_PWM */ #define PALMAS_LED_PERIOD_CTRL … #define PALMAS_LED_CTRL … #define PALMAS_PWM_CTRL1 … #define PALMAS_PWM_CTRL2 … /* Bit definitions for LED_PERIOD_CTRL */ #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK … #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT … #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK … #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT … /* Bit definitions for LED_CTRL */ #define PALMAS_LED_CTRL_LED_2_SEQ … #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT … #define PALMAS_LED_CTRL_LED_1_SEQ … #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT … #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK … #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT … #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK … #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT … /* Bit definitions for PWM_CTRL1 */ #define PALMAS_PWM_CTRL1_PWM_FREQ_EN … #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT … #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL … #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT … /* Bit definitions for PWM_CTRL2 */ #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK … #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT … /* Registers for function INTERRUPT */ #define PALMAS_INT1_STATUS … #define PALMAS_INT1_MASK … #define PALMAS_INT1_LINE_STATE … #define PALMAS_INT1_EDGE_DETECT1_RESERVED … #define PALMAS_INT1_EDGE_DETECT2_RESERVED … #define PALMAS_INT2_STATUS … #define PALMAS_INT2_MASK … #define PALMAS_INT2_LINE_STATE … #define PALMAS_INT2_EDGE_DETECT1_RESERVED … #define PALMAS_INT2_EDGE_DETECT2_RESERVED … #define PALMAS_INT3_STATUS … #define PALMAS_INT3_MASK … #define PALMAS_INT3_LINE_STATE … #define PALMAS_INT3_EDGE_DETECT1_RESERVED … #define PALMAS_INT3_EDGE_DETECT2_RESERVED … #define PALMAS_INT4_STATUS … #define PALMAS_INT4_MASK … #define PALMAS_INT4_LINE_STATE … #define PALMAS_INT4_EDGE_DETECT1 … #define PALMAS_INT4_EDGE_DETECT2 … #define PALMAS_INT_CTRL … /* Bit definitions for INT1_STATUS */ #define PALMAS_INT1_STATUS_VBAT_MON … #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT … #define PALMAS_INT1_STATUS_VSYS_MON … #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT … #define PALMAS_INT1_STATUS_HOTDIE … #define PALMAS_INT1_STATUS_HOTDIE_SHIFT … #define PALMAS_INT1_STATUS_PWRDOWN … #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT … #define PALMAS_INT1_STATUS_RPWRON … #define PALMAS_INT1_STATUS_RPWRON_SHIFT … #define PALMAS_INT1_STATUS_LONG_PRESS_KEY … #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT … #define PALMAS_INT1_STATUS_PWRON … #define PALMAS_INT1_STATUS_PWRON_SHIFT … #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV … #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT … /* Bit definitions for INT1_MASK */ #define PALMAS_INT1_MASK_VBAT_MON … #define PALMAS_INT1_MASK_VBAT_MON_SHIFT … #define PALMAS_INT1_MASK_VSYS_MON … #define PALMAS_INT1_MASK_VSYS_MON_SHIFT … #define PALMAS_INT1_MASK_HOTDIE … #define PALMAS_INT1_MASK_HOTDIE_SHIFT … #define PALMAS_INT1_MASK_PWRDOWN … #define PALMAS_INT1_MASK_PWRDOWN_SHIFT … #define PALMAS_INT1_MASK_RPWRON … #define PALMAS_INT1_MASK_RPWRON_SHIFT … #define PALMAS_INT1_MASK_LONG_PRESS_KEY … #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT … #define PALMAS_INT1_MASK_PWRON … #define PALMAS_INT1_MASK_PWRON_SHIFT … #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV … #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT … /* Bit definitions for INT1_LINE_STATE */ #define PALMAS_INT1_LINE_STATE_VBAT_MON … #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT … #define PALMAS_INT1_LINE_STATE_VSYS_MON … #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT … #define PALMAS_INT1_LINE_STATE_HOTDIE … #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT … #define PALMAS_INT1_LINE_STATE_PWRDOWN … #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT … #define PALMAS_INT1_LINE_STATE_RPWRON … #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT … #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY … #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT … #define PALMAS_INT1_LINE_STATE_PWRON … #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT … #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV … #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT … /* Bit definitions for INT2_STATUS */ #define PALMAS_INT2_STATUS_VAC_ACOK … #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT … #define PALMAS_INT2_STATUS_SHORT … #define PALMAS_INT2_STATUS_SHORT_SHIFT … #define PALMAS_INT2_STATUS_FBI_BB … #define PALMAS_INT2_STATUS_FBI_BB_SHIFT … #define PALMAS_INT2_STATUS_RESET_IN … #define PALMAS_INT2_STATUS_RESET_IN_SHIFT … #define PALMAS_INT2_STATUS_BATREMOVAL … #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT … #define PALMAS_INT2_STATUS_WDT … #define PALMAS_INT2_STATUS_WDT_SHIFT … #define PALMAS_INT2_STATUS_RTC_TIMER … #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT … #define PALMAS_INT2_STATUS_RTC_ALARM … #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT … /* Bit definitions for INT2_MASK */ #define PALMAS_INT2_MASK_VAC_ACOK … #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT … #define PALMAS_INT2_MASK_SHORT … #define PALMAS_INT2_MASK_SHORT_SHIFT … #define PALMAS_INT2_MASK_FBI_BB … #define PALMAS_INT2_MASK_FBI_BB_SHIFT … #define PALMAS_INT2_MASK_RESET_IN … #define PALMAS_INT2_MASK_RESET_IN_SHIFT … #define PALMAS_INT2_MASK_BATREMOVAL … #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT … #define PALMAS_INT2_MASK_WDT … #define PALMAS_INT2_MASK_WDT_SHIFT … #define PALMAS_INT2_MASK_RTC_TIMER … #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT … #define PALMAS_INT2_MASK_RTC_ALARM … #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT … /* Bit definitions for INT2_LINE_STATE */ #define PALMAS_INT2_LINE_STATE_VAC_ACOK … #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT … #define PALMAS_INT2_LINE_STATE_SHORT … #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT … #define PALMAS_INT2_LINE_STATE_FBI_BB … #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT … #define PALMAS_INT2_LINE_STATE_RESET_IN … #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT … #define PALMAS_INT2_LINE_STATE_BATREMOVAL … #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT … #define PALMAS_INT2_LINE_STATE_WDT … #define PALMAS_INT2_LINE_STATE_WDT_SHIFT … #define PALMAS_INT2_LINE_STATE_RTC_TIMER … #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT … #define PALMAS_INT2_LINE_STATE_RTC_ALARM … #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT … /* Bit definitions for INT3_STATUS */ #define PALMAS_INT3_STATUS_VBUS … #define PALMAS_INT3_STATUS_VBUS_SHIFT … #define PALMAS_INT3_STATUS_VBUS_OTG … #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT … #define PALMAS_INT3_STATUS_ID … #define PALMAS_INT3_STATUS_ID_SHIFT … #define PALMAS_INT3_STATUS_ID_OTG … #define PALMAS_INT3_STATUS_ID_OTG_SHIFT … #define PALMAS_INT3_STATUS_GPADC_EOC_RT … #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT … #define PALMAS_INT3_STATUS_GPADC_EOC_SW … #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT … #define PALMAS_INT3_STATUS_GPADC_AUTO_1 … #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT … #define PALMAS_INT3_STATUS_GPADC_AUTO_0 … #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT … /* Bit definitions for INT3_MASK */ #define PALMAS_INT3_MASK_VBUS … #define PALMAS_INT3_MASK_VBUS_SHIFT … #define PALMAS_INT3_MASK_VBUS_OTG … #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT … #define PALMAS_INT3_MASK_ID … #define PALMAS_INT3_MASK_ID_SHIFT … #define PALMAS_INT3_MASK_ID_OTG … #define PALMAS_INT3_MASK_ID_OTG_SHIFT … #define PALMAS_INT3_MASK_GPADC_EOC_RT … #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT … #define PALMAS_INT3_MASK_GPADC_EOC_SW … #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT … #define PALMAS_INT3_MASK_GPADC_AUTO_1 … #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT … #define PALMAS_INT3_MASK_GPADC_AUTO_0 … #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT … /* Bit definitions for INT3_LINE_STATE */ #define PALMAS_INT3_LINE_STATE_VBUS … #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT … #define PALMAS_INT3_LINE_STATE_VBUS_OTG … #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT … #define PALMAS_INT3_LINE_STATE_ID … #define PALMAS_INT3_LINE_STATE_ID_SHIFT … #define PALMAS_INT3_LINE_STATE_ID_OTG … #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT … #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT … #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT … #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW … #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT … #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 … #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT … #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 … #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT … /* Bit definitions for INT4_STATUS */ #define PALMAS_INT4_STATUS_GPIO_7 … #define PALMAS_INT4_STATUS_GPIO_7_SHIFT … #define PALMAS_INT4_STATUS_GPIO_6 … #define PALMAS_INT4_STATUS_GPIO_6_SHIFT … #define PALMAS_INT4_STATUS_GPIO_5 … #define PALMAS_INT4_STATUS_GPIO_5_SHIFT … #define PALMAS_INT4_STATUS_GPIO_4 … #define PALMAS_INT4_STATUS_GPIO_4_SHIFT … #define PALMAS_INT4_STATUS_GPIO_3 … #define PALMAS_INT4_STATUS_GPIO_3_SHIFT … #define PALMAS_INT4_STATUS_GPIO_2 … #define PALMAS_INT4_STATUS_GPIO_2_SHIFT … #define PALMAS_INT4_STATUS_GPIO_1 … #define PALMAS_INT4_STATUS_GPIO_1_SHIFT … #define PALMAS_INT4_STATUS_GPIO_0 … #define PALMAS_INT4_STATUS_GPIO_0_SHIFT … /* Bit definitions for INT4_MASK */ #define PALMAS_INT4_MASK_GPIO_7 … #define PALMAS_INT4_MASK_GPIO_7_SHIFT … #define PALMAS_INT4_MASK_GPIO_6 … #define PALMAS_INT4_MASK_GPIO_6_SHIFT … #define PALMAS_INT4_MASK_GPIO_5 … #define PALMAS_INT4_MASK_GPIO_5_SHIFT … #define PALMAS_INT4_MASK_GPIO_4 … #define PALMAS_INT4_MASK_GPIO_4_SHIFT … #define PALMAS_INT4_MASK_GPIO_3 … #define PALMAS_INT4_MASK_GPIO_3_SHIFT … #define PALMAS_INT4_MASK_GPIO_2 … #define PALMAS_INT4_MASK_GPIO_2_SHIFT … #define PALMAS_INT4_MASK_GPIO_1 … #define PALMAS_INT4_MASK_GPIO_1_SHIFT … #define PALMAS_INT4_MASK_GPIO_0 … #define PALMAS_INT4_MASK_GPIO_0_SHIFT … /* Bit definitions for INT4_LINE_STATE */ #define PALMAS_INT4_LINE_STATE_GPIO_7 … #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT … #define PALMAS_INT4_LINE_STATE_GPIO_6 … #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT … #define PALMAS_INT4_LINE_STATE_GPIO_5 … #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT … #define PALMAS_INT4_LINE_STATE_GPIO_4 … #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT … #define PALMAS_INT4_LINE_STATE_GPIO_3 … #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT … #define PALMAS_INT4_LINE_STATE_GPIO_2 … #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT … #define PALMAS_INT4_LINE_STATE_GPIO_1 … #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT … #define PALMAS_INT4_LINE_STATE_GPIO_0 … #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT … /* Bit definitions for INT4_EDGE_DETECT1 */ #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING … #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT … #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING … #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT … #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING … #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT … #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING … #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT … #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING … #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT … #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING … #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT … #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING … #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT … #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING … #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT … /* Bit definitions for INT4_EDGE_DETECT2 */ #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING … #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT … #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING … #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT … #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING … #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT … #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING … #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT … #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING … #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT … #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING … #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT … #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING … #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT … #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING … #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT … /* Bit definitions for INT_CTRL */ #define PALMAS_INT_CTRL_INT_PENDING … #define PALMAS_INT_CTRL_INT_PENDING_SHIFT … #define PALMAS_INT_CTRL_INT_CLEAR … #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT … /* Registers for function USB_OTG */ #define PALMAS_USB_WAKEUP … #define PALMAS_USB_VBUS_CTRL_SET … #define PALMAS_USB_VBUS_CTRL_CLR … #define PALMAS_USB_ID_CTRL_SET … #define PALMAS_USB_ID_CTRL_CLEAR … #define PALMAS_USB_VBUS_INT_SRC … #define PALMAS_USB_VBUS_INT_LATCH_SET … #define PALMAS_USB_VBUS_INT_LATCH_CLR … #define PALMAS_USB_VBUS_INT_EN_LO_SET … #define PALMAS_USB_VBUS_INT_EN_LO_CLR … #define PALMAS_USB_VBUS_INT_EN_HI_SET … #define PALMAS_USB_VBUS_INT_EN_HI_CLR … #define PALMAS_USB_ID_INT_SRC … #define PALMAS_USB_ID_INT_LATCH_SET … #define PALMAS_USB_ID_INT_LATCH_CLR … #define PALMAS_USB_ID_INT_EN_LO_SET … #define PALMAS_USB_ID_INT_EN_LO_CLR … #define PALMAS_USB_ID_INT_EN_HI_SET … #define PALMAS_USB_ID_INT_EN_HI_CLR … #define PALMAS_USB_OTG_ADP_CTRL … #define PALMAS_USB_OTG_ADP_HIGH … #define PALMAS_USB_OTG_ADP_LOW … #define PALMAS_USB_OTG_ADP_RISE … #define PALMAS_USB_OTG_REVISION … /* Bit definitions for USB_WAKEUP */ #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP … #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT … /* Bit definitions for USB_VBUS_CTRL_SET */ #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS … #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT … #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG … #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT … #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC … #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT … #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK … #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT … #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP … #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT … /* Bit definitions for USB_VBUS_CTRL_CLR */ #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS … #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT … #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG … #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT … #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC … #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT … #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK … #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT … #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP … #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT … /* Bit definitions for USB_ID_CTRL_SET */ #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K … #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT … #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K … #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT … #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV … #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT … #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U … #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT … #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U … #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT … #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP … #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT … /* Bit definitions for USB_ID_CTRL_CLEAR */ #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K … #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT … #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K … #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT … #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV … #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT … #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U … #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT … #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U … #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT … #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP … #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT … /* Bit definitions for USB_VBUS_INT_SRC */ #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD … #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB … #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT … #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS … #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT … #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD … #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD … #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD … #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END … #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT … /* Bit definitions for USB_VBUS_INT_LATCH_SET */ #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD … #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB … #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS … #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP … #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD … #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD … #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD … #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END … #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT … /* Bit definitions for USB_VBUS_INT_LATCH_CLR */ #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD … #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB … #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS … #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP … #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD … #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD … #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD … #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END … #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT … /* Bit definitions for USB_VBUS_INT_EN_LO_SET */ #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD … #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB … #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT … #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS … #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT … #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD … #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD … #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD … #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END … #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT … /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD … #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB … #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT … #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS … #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT … #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD … #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD … #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD … #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END … #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT … /* Bit definitions for USB_VBUS_INT_EN_HI_SET */ #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD … #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB … #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS … #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP … #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD … #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD … #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD … #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END … #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT … /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END … #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT … /* Bit definitions for USB_ID_INT_SRC */ #define PALMAS_USB_ID_INT_SRC_ID_FLOAT … #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT … #define PALMAS_USB_ID_INT_SRC_ID_A … #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT … #define PALMAS_USB_ID_INT_SRC_ID_B … #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT … #define PALMAS_USB_ID_INT_SRC_ID_C … #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT … #define PALMAS_USB_ID_INT_SRC_ID_GND … #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT … /* Bit definitions for USB_ID_INT_LATCH_SET */ #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT … #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT … #define PALMAS_USB_ID_INT_LATCH_SET_ID_A … #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT … #define PALMAS_USB_ID_INT_LATCH_SET_ID_B … #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT … #define PALMAS_USB_ID_INT_LATCH_SET_ID_C … #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT … #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND … #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT … /* Bit definitions for USB_ID_INT_LATCH_CLR */ #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT … #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT … #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A … #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT … #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B … #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT … #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C … #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT … #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND … #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT … /* Bit definitions for USB_ID_INT_EN_LO_SET */ #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT … #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT … #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A … #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT … #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B … #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT … #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C … #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT … #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND … #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT … /* Bit definitions for USB_ID_INT_EN_LO_CLR */ #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT … #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT … #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A … #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT … #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B … #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT … #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C … #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT … #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND … #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT … /* Bit definitions for USB_ID_INT_EN_HI_SET */ #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT … #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT … #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A … #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT … #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B … #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT … #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C … #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT … #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND … #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT … /* Bit definitions for USB_ID_INT_EN_HI_CLR */ #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT … #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT … #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A … #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT … #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B … #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT … #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C … #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT … #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND … #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT … /* Bit definitions for USB_OTG_ADP_CTRL */ #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN … #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT … #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK … #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT … /* Bit definitions for USB_OTG_ADP_HIGH */ #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK … #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT … /* Bit definitions for USB_OTG_ADP_LOW */ #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK … #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT … /* Bit definitions for USB_OTG_ADP_RISE */ #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK … #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT … /* Bit definitions for USB_OTG_REVISION */ #define PALMAS_USB_OTG_REVISION_OTG_REV … #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT … /* Registers for function VIBRATOR */ #define PALMAS_VIBRA_CTRL … /* Bit definitions for VIBRA_CTRL */ #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK … #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT … #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL … #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT … /* Registers for function GPIO */ #define PALMAS_GPIO_DATA_IN … #define PALMAS_GPIO_DATA_DIR … #define PALMAS_GPIO_DATA_OUT … #define PALMAS_GPIO_DEBOUNCE_EN … #define PALMAS_GPIO_CLEAR_DATA_OUT … #define PALMAS_GPIO_SET_DATA_OUT … #define PALMAS_PU_PD_GPIO_CTRL1 … #define PALMAS_PU_PD_GPIO_CTRL2 … #define PALMAS_OD_OUTPUT_GPIO_CTRL … #define PALMAS_GPIO_DATA_IN2 … #define PALMAS_GPIO_DATA_DIR2 … #define PALMAS_GPIO_DATA_OUT2 … #define PALMAS_GPIO_DEBOUNCE_EN2 … #define PALMAS_GPIO_CLEAR_DATA_OUT2 … #define PALMAS_GPIO_SET_DATA_OUT2 … #define PALMAS_PU_PD_GPIO_CTRL3 … #define PALMAS_PU_PD_GPIO_CTRL4 … #define PALMAS_OD_OUTPUT_GPIO_CTRL2 … /* Bit definitions for GPIO_DATA_IN */ #define PALMAS_GPIO_DATA_IN_GPIO_7_IN … #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT … #define PALMAS_GPIO_DATA_IN_GPIO_6_IN … #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT … #define PALMAS_GPIO_DATA_IN_GPIO_5_IN … #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT … #define PALMAS_GPIO_DATA_IN_GPIO_4_IN … #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT … #define PALMAS_GPIO_DATA_IN_GPIO_3_IN … #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT … #define PALMAS_GPIO_DATA_IN_GPIO_2_IN … #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT … #define PALMAS_GPIO_DATA_IN_GPIO_1_IN … #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT … #define PALMAS_GPIO_DATA_IN_GPIO_0_IN … #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT … /* Bit definitions for GPIO_DATA_DIR */ #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR … #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT … #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR … #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT … #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR … #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT … #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR … #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT … #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR … #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT … #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR … #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT … #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR … #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT … #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR … #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT … /* Bit definitions for GPIO_DATA_OUT */ #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT … #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT … #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT … #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT … #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT … #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT … #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT … #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT … #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT … #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT … #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT … #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT … #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT … #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT … #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT … #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT … /* Bit definitions for GPIO_DEBOUNCE_EN */ #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN … #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT … /* Bit definitions for GPIO_CLEAR_DATA_OUT */ #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT … #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT … /* Bit definitions for GPIO_SET_DATA_OUT */ #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT … #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT … /* Bit definitions for PU_PD_GPIO_CTRL1 */ #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD … #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT … #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU … #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT … #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD … #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT … #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU … #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT … #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD … #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT … #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD … #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT … /* Bit definitions for PU_PD_GPIO_CTRL2 */ #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD … #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT … #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU … #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT … #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD … #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT … #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU … #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT … #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD … #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT … #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU … #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT … #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD … #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT … /* Bit definitions for OD_OUTPUT_GPIO_CTRL */ #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD … #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT … #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD … #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT … #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD … #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT … /* Registers for function GPADC */ #define PALMAS_GPADC_CTRL1 … #define PALMAS_GPADC_CTRL2 … #define PALMAS_GPADC_RT_CTRL … #define PALMAS_GPADC_AUTO_CTRL … #define PALMAS_GPADC_STATUS … #define PALMAS_GPADC_RT_SELECT … #define PALMAS_GPADC_RT_CONV0_LSB … #define PALMAS_GPADC_RT_CONV0_MSB … #define PALMAS_GPADC_AUTO_SELECT … #define PALMAS_GPADC_AUTO_CONV0_LSB … #define PALMAS_GPADC_AUTO_CONV0_MSB … #define PALMAS_GPADC_AUTO_CONV1_LSB … #define PALMAS_GPADC_AUTO_CONV1_MSB … #define PALMAS_GPADC_SW_SELECT … #define PALMAS_GPADC_SW_CONV0_LSB … #define PALMAS_GPADC_SW_CONV0_MSB … #define PALMAS_GPADC_THRES_CONV0_LSB … #define PALMAS_GPADC_THRES_CONV0_MSB … #define PALMAS_GPADC_THRES_CONV1_LSB … #define PALMAS_GPADC_THRES_CONV1_MSB … #define PALMAS_GPADC_SMPS_ILMONITOR_EN … #define PALMAS_GPADC_SMPS_VSEL_MONITORING … /* Bit definitions for GPADC_CTRL1 */ #define PALMAS_GPADC_CTRL1_RESERVED_MASK … #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT … #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK … #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT … #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK … #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT … #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET … #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT … #define PALMAS_GPADC_CTRL1_GPADC_FORCE … #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT … /* Bit definitions for GPADC_CTRL2 */ #define PALMAS_GPADC_CTRL2_RESERVED_MASK … #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT … /* Bit definitions for GPADC_RT_CTRL */ #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY … #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT … #define PALMAS_GPADC_RT_CTRL_START_POLARITY … #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT … /* Bit definitions for GPADC_AUTO_CTRL */ #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 … #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT … #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 … #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT … #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN … #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT … #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN … #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT … #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK … #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT … /* Bit definitions for GPADC_STATUS */ #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE … #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT … /* Bit definitions for GPADC_RT_SELECT */ #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN … #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT … #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK … #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT … /* Bit definitions for GPADC_RT_CONV0_LSB */ #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK … #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT … /* Bit definitions for GPADC_RT_CONV0_MSB */ #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK … #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT … /* Bit definitions for GPADC_AUTO_SELECT */ #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK … #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT … #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK … #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT … /* Bit definitions for GPADC_AUTO_CONV0_LSB */ #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK … #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT … /* Bit definitions for GPADC_AUTO_CONV0_MSB */ #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK … #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT … /* Bit definitions for GPADC_AUTO_CONV1_LSB */ #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK … #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT … /* Bit definitions for GPADC_AUTO_CONV1_MSB */ #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK … #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT … /* Bit definitions for GPADC_SW_SELECT */ #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN … #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT … #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 … #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT … #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK … #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT … /* Bit definitions for GPADC_SW_CONV0_LSB */ #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK … #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT … /* Bit definitions for GPADC_SW_CONV0_MSB */ #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK … #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT … /* Bit definitions for GPADC_THRES_CONV0_LSB */ #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK … #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT … /* Bit definitions for GPADC_THRES_CONV0_MSB */ #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL … #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT … #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK … #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT … /* Bit definitions for GPADC_THRES_CONV1_LSB */ #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK … #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT … /* Bit definitions for GPADC_THRES_CONV1_MSB */ #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL … #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT … #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK … #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT … /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN … #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT … #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT … #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT … #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK … #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT … /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE … #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT … #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK … #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT … /* Registers for function GPADC */ #define PALMAS_GPADC_TRIM1 … #define PALMAS_GPADC_TRIM2 … #define PALMAS_GPADC_TRIM3 … #define PALMAS_GPADC_TRIM4 … #define PALMAS_GPADC_TRIM5 … #define PALMAS_GPADC_TRIM6 … #define PALMAS_GPADC_TRIM7 … #define PALMAS_GPADC_TRIM8 … #define PALMAS_GPADC_TRIM9 … #define PALMAS_GPADC_TRIM10 … #define PALMAS_GPADC_TRIM11 … #define PALMAS_GPADC_TRIM12 … #define PALMAS_GPADC_TRIM13 … #define PALMAS_GPADC_TRIM14 … #define PALMAS_GPADC_TRIM15 … #define PALMAS_GPADC_TRIM16 … /* TPS659038 regen2_ctrl offset iss different from palmas */ #define TPS659038_REGEN2_CTRL … /* TPS65917 Interrupt registers */ /* Registers for function INTERRUPT */ #define TPS65917_INT1_STATUS … #define TPS65917_INT1_MASK … #define TPS65917_INT1_LINE_STATE … #define TPS65917_INT2_STATUS … #define TPS65917_INT2_MASK … #define TPS65917_INT2_LINE_STATE … #define TPS65917_INT3_STATUS … #define TPS65917_INT3_MASK … #define TPS65917_INT3_LINE_STATE … #define TPS65917_INT4_STATUS … #define TPS65917_INT4_MASK … #define TPS65917_INT4_LINE_STATE … #define TPS65917_INT4_EDGE_DETECT1 … #define TPS65917_INT4_EDGE_DETECT2 … #define TPS65917_INT_CTRL … /* Bit definitions for INT1_STATUS */ #define TPS65917_INT1_STATUS_VSYS_MON … #define TPS65917_INT1_STATUS_VSYS_MON_SHIFT … #define TPS65917_INT1_STATUS_HOTDIE … #define TPS65917_INT1_STATUS_HOTDIE_SHIFT … #define TPS65917_INT1_STATUS_PWRDOWN … #define TPS65917_INT1_STATUS_PWRDOWN_SHIFT … #define TPS65917_INT1_STATUS_LONG_PRESS_KEY … #define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT … #define TPS65917_INT1_STATUS_PWRON … #define TPS65917_INT1_STATUS_PWRON_SHIFT … /* Bit definitions for INT1_MASK */ #define TPS65917_INT1_MASK_VSYS_MON … #define TPS65917_INT1_MASK_VSYS_MON_SHIFT … #define TPS65917_INT1_MASK_HOTDIE … #define TPS65917_INT1_MASK_HOTDIE_SHIFT … #define TPS65917_INT1_MASK_PWRDOWN … #define TPS65917_INT1_MASK_PWRDOWN_SHIFT … #define TPS65917_INT1_MASK_LONG_PRESS_KEY … #define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT … #define TPS65917_INT1_MASK_PWRON … #define TPS65917_INT1_MASK_PWRON_SHIFT … /* Bit definitions for INT1_LINE_STATE */ #define TPS65917_INT1_LINE_STATE_VSYS_MON … #define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT … #define TPS65917_INT1_LINE_STATE_HOTDIE … #define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT … #define TPS65917_INT1_LINE_STATE_PWRDOWN … #define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT … #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY … #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT … #define TPS65917_INT1_LINE_STATE_PWRON … #define TPS65917_INT1_LINE_STATE_PWRON_SHIFT … /* Bit definitions for INT2_STATUS */ #define TPS65917_INT2_STATUS_SHORT … #define TPS65917_INT2_STATUS_SHORT_SHIFT … #define TPS65917_INT2_STATUS_FSD … #define TPS65917_INT2_STATUS_FSD_SHIFT … #define TPS65917_INT2_STATUS_RESET_IN … #define TPS65917_INT2_STATUS_RESET_IN_SHIFT … #define TPS65917_INT2_STATUS_WDT … #define TPS65917_INT2_STATUS_WDT_SHIFT … #define TPS65917_INT2_STATUS_OTP_ERROR … #define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT … /* Bit definitions for INT2_MASK */ #define TPS65917_INT2_MASK_SHORT … #define TPS65917_INT2_MASK_SHORT_SHIFT … #define TPS65917_INT2_MASK_FSD … #define TPS65917_INT2_MASK_FSD_SHIFT … #define TPS65917_INT2_MASK_RESET_IN … #define TPS65917_INT2_MASK_RESET_IN_SHIFT … #define TPS65917_INT2_MASK_WDT … #define TPS65917_INT2_MASK_WDT_SHIFT … #define TPS65917_INT2_MASK_OTP_ERROR_TIMER … #define TPS65917_INT2_MASK_OTP_ERROR_SHIFT … /* Bit definitions for INT2_LINE_STATE */ #define TPS65917_INT2_LINE_STATE_SHORT … #define TPS65917_INT2_LINE_STATE_SHORT_SHIFT … #define TPS65917_INT2_LINE_STATE_FSD … #define TPS65917_INT2_LINE_STATE_FSD_SHIFT … #define TPS65917_INT2_LINE_STATE_RESET_IN … #define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT … #define TPS65917_INT2_LINE_STATE_WDT … #define TPS65917_INT2_LINE_STATE_WDT_SHIFT … #define TPS65917_INT2_LINE_STATE_OTP_ERROR … #define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT … /* Bit definitions for INT3_STATUS */ #define TPS65917_INT3_STATUS_VBUS … #define TPS65917_INT3_STATUS_VBUS_SHIFT … #define TPS65917_INT3_STATUS_GPADC_EOC_SW … #define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT … #define TPS65917_INT3_STATUS_GPADC_AUTO_1 … #define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT … #define TPS65917_INT3_STATUS_GPADC_AUTO_0 … #define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT … /* Bit definitions for INT3_MASK */ #define TPS65917_INT3_MASK_VBUS … #define TPS65917_INT3_MASK_VBUS_SHIFT … #define TPS65917_INT3_MASK_GPADC_EOC_SW … #define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT … #define TPS65917_INT3_MASK_GPADC_AUTO_1 … #define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT … #define TPS65917_INT3_MASK_GPADC_AUTO_0 … #define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT … /* Bit definitions for INT3_LINE_STATE */ #define TPS65917_INT3_LINE_STATE_VBUS … #define TPS65917_INT3_LINE_STATE_VBUS_SHIFT … #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW … #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT … #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 … #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT … #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 … #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT … /* Bit definitions for INT4_STATUS */ #define TPS65917_INT4_STATUS_GPIO_6 … #define TPS65917_INT4_STATUS_GPIO_6_SHIFT … #define TPS65917_INT4_STATUS_GPIO_5 … #define TPS65917_INT4_STATUS_GPIO_5_SHIFT … #define TPS65917_INT4_STATUS_GPIO_4 … #define TPS65917_INT4_STATUS_GPIO_4_SHIFT … #define TPS65917_INT4_STATUS_GPIO_3 … #define TPS65917_INT4_STATUS_GPIO_3_SHIFT … #define TPS65917_INT4_STATUS_GPIO_2 … #define TPS65917_INT4_STATUS_GPIO_2_SHIFT … #define TPS65917_INT4_STATUS_GPIO_1 … #define TPS65917_INT4_STATUS_GPIO_1_SHIFT … #define TPS65917_INT4_STATUS_GPIO_0 … #define TPS65917_INT4_STATUS_GPIO_0_SHIFT … /* Bit definitions for INT4_MASK */ #define TPS65917_INT4_MASK_GPIO_6 … #define TPS65917_INT4_MASK_GPIO_6_SHIFT … #define TPS65917_INT4_MASK_GPIO_5 … #define TPS65917_INT4_MASK_GPIO_5_SHIFT … #define TPS65917_INT4_MASK_GPIO_4 … #define TPS65917_INT4_MASK_GPIO_4_SHIFT … #define TPS65917_INT4_MASK_GPIO_3 … #define TPS65917_INT4_MASK_GPIO_3_SHIFT … #define TPS65917_INT4_MASK_GPIO_2 … #define TPS65917_INT4_MASK_GPIO_2_SHIFT … #define TPS65917_INT4_MASK_GPIO_1 … #define TPS65917_INT4_MASK_GPIO_1_SHIFT … #define TPS65917_INT4_MASK_GPIO_0 … #define TPS65917_INT4_MASK_GPIO_0_SHIFT … /* Bit definitions for INT4_LINE_STATE */ #define TPS65917_INT4_LINE_STATE_GPIO_6 … #define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT … #define TPS65917_INT4_LINE_STATE_GPIO_5 … #define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT … #define TPS65917_INT4_LINE_STATE_GPIO_4 … #define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT … #define TPS65917_INT4_LINE_STATE_GPIO_3 … #define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT … #define TPS65917_INT4_LINE_STATE_GPIO_2 … #define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT … #define TPS65917_INT4_LINE_STATE_GPIO_1 … #define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT … #define TPS65917_INT4_LINE_STATE_GPIO_0 … #define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT … /* Bit definitions for INT4_EDGE_DETECT1 */ #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING … #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT … #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING … #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT … #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING … #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT … #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING … #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT … #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING … #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT … #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING … #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT … #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING … #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT … #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING … #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT … /* Bit definitions for INT4_EDGE_DETECT2 */ #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING … #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT … #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING … #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT … #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING … #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT … #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING … #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT … #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING … #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT … #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING … #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT … /* Bit definitions for INT_CTRL */ #define TPS65917_INT_CTRL_INT_PENDING … #define TPS65917_INT_CTRL_INT_PENDING_SHIFT … #define TPS65917_INT_CTRL_INT_CLEAR … #define TPS65917_INT_CTRL_INT_CLEAR_SHIFT … /* TPS65917 SMPS Registers */ /* Registers for function SMPS */ #define TPS65917_SMPS1_CTRL … #define TPS65917_SMPS1_FORCE … #define TPS65917_SMPS1_VOLTAGE … #define TPS65917_SMPS2_CTRL … #define TPS65917_SMPS2_FORCE … #define TPS65917_SMPS2_VOLTAGE … #define TPS65917_SMPS3_CTRL … #define TPS65917_SMPS3_FORCE … #define TPS65917_SMPS3_VOLTAGE … #define TPS65917_SMPS4_CTRL … #define TPS65917_SMPS4_VOLTAGE … #define TPS65917_SMPS5_CTRL … #define TPS65917_SMPS5_VOLTAGE … #define TPS65917_SMPS_CTRL … #define TPS65917_SMPS_PD_CTRL … #define TPS65917_SMPS_THERMAL_EN … #define TPS65917_SMPS_THERMAL_STATUS … #define TPS65917_SMPS_SHORT_STATUS … #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN … #define TPS65917_SMPS_POWERGOOD_MASK1 … #define TPS65917_SMPS_POWERGOOD_MASK2 … /* Bit definitions for SMPS1_CTRL */ #define TPS65917_SMPS1_CTRL_WR_S … #define TPS65917_SMPS1_CTRL_WR_S_SHIFT … #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN … #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT … #define TPS65917_SMPS1_CTRL_STATUS_MASK … #define TPS65917_SMPS1_CTRL_STATUS_SHIFT … #define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK … #define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK … #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SMPS1_FORCE */ #define TPS65917_SMPS1_FORCE_CMD … #define TPS65917_SMPS1_FORCE_CMD_SHIFT … #define TPS65917_SMPS1_FORCE_VSEL_MASK … #define TPS65917_SMPS1_FORCE_VSEL_SHIFT … /* Bit definitions for SMPS1_VOLTAGE */ #define TPS65917_SMPS1_VOLTAGE_RANGE … #define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT … #define TPS65917_SMPS1_VOLTAGE_VSEL_MASK … #define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT … /* Bit definitions for SMPS2_CTRL */ #define TPS65917_SMPS2_CTRL_WR_S … #define TPS65917_SMPS2_CTRL_WR_S_SHIFT … #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN … #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT … #define TPS65917_SMPS2_CTRL_STATUS_MASK … #define TPS65917_SMPS2_CTRL_STATUS_SHIFT … #define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK … #define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK … #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SMPS2_FORCE */ #define TPS65917_SMPS2_FORCE_CMD … #define TPS65917_SMPS2_FORCE_CMD_SHIFT … #define TPS65917_SMPS2_FORCE_VSEL_MASK … #define TPS65917_SMPS2_FORCE_VSEL_SHIFT … /* Bit definitions for SMPS2_VOLTAGE */ #define TPS65917_SMPS2_VOLTAGE_RANGE … #define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT … #define TPS65917_SMPS2_VOLTAGE_VSEL_MASK … #define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT … /* Bit definitions for SMPS3_CTRL */ #define TPS65917_SMPS3_CTRL_WR_S … #define TPS65917_SMPS3_CTRL_WR_S_SHIFT … #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN … #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT … #define TPS65917_SMPS3_CTRL_STATUS_MASK … #define TPS65917_SMPS3_CTRL_STATUS_SHIFT … #define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK … #define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK … #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SMPS3_FORCE */ #define TPS65917_SMPS3_FORCE_CMD … #define TPS65917_SMPS3_FORCE_CMD_SHIFT … #define TPS65917_SMPS3_FORCE_VSEL_MASK … #define TPS65917_SMPS3_FORCE_VSEL_SHIFT … /* Bit definitions for SMPS3_VOLTAGE */ #define TPS65917_SMPS3_VOLTAGE_RANGE … #define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT … #define TPS65917_SMPS3_VOLTAGE_VSEL_MASK … #define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT … /* Bit definitions for SMPS4_CTRL */ #define TPS65917_SMPS4_CTRL_WR_S … #define TPS65917_SMPS4_CTRL_WR_S_SHIFT … #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN … #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT … #define TPS65917_SMPS4_CTRL_STATUS_MASK … #define TPS65917_SMPS4_CTRL_STATUS_SHIFT … #define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK … #define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK … #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SMPS4_VOLTAGE */ #define TPS65917_SMPS4_VOLTAGE_RANGE … #define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT … #define TPS65917_SMPS4_VOLTAGE_VSEL_MASK … #define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT … /* Bit definitions for SMPS5_CTRL */ #define TPS65917_SMPS5_CTRL_WR_S … #define TPS65917_SMPS5_CTRL_WR_S_SHIFT … #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN … #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT … #define TPS65917_SMPS5_CTRL_STATUS_MASK … #define TPS65917_SMPS5_CTRL_STATUS_SHIFT … #define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK … #define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK … #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for SMPS5_VOLTAGE */ #define TPS65917_SMPS5_VOLTAGE_RANGE … #define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT … #define TPS65917_SMPS5_VOLTAGE_VSEL_MASK … #define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT … /* Bit definitions for SMPS_CTRL */ #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN … #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT … #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL … #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT … /* Bit definitions for SMPS_PD_CTRL */ #define TPS65917_SMPS_PD_CTRL_SMPS5 … #define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT … #define TPS65917_SMPS_PD_CTRL_SMPS4 … #define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT … #define TPS65917_SMPS_PD_CTRL_SMPS3 … #define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT … #define TPS65917_SMPS_PD_CTRL_SMPS2 … #define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT … #define TPS65917_SMPS_PD_CTRL_SMPS1 … #define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT … /* Bit definitions for SMPS_THERMAL_EN */ #define TPS65917_SMPS_THERMAL_EN_SMPS5 … #define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT … #define TPS65917_SMPS_THERMAL_EN_SMPS3 … #define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT … #define TPS65917_SMPS_THERMAL_EN_SMPS12 … #define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT … /* Bit definitions for SMPS_THERMAL_STATUS */ #define TPS65917_SMPS_THERMAL_STATUS_SMPS5 … #define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT … #define TPS65917_SMPS_THERMAL_STATUS_SMPS3 … #define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT … #define TPS65917_SMPS_THERMAL_STATUS_SMPS12 … #define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT … /* Bit definitions for SMPS_SHORT_STATUS */ #define TPS65917_SMPS_SHORT_STATUS_SMPS5 … #define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT … #define TPS65917_SMPS_SHORT_STATUS_SMPS4 … #define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT … #define TPS65917_SMPS_SHORT_STATUS_SMPS3 … #define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT … #define TPS65917_SMPS_SHORT_STATUS_SMPS2 … #define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT … #define TPS65917_SMPS_SHORT_STATUS_SMPS1 … #define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT … /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 … #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT … #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 … #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT … #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 … #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT … #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 … #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT … #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 … #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT … /* Bit definitions for SMPS_POWERGOOD_MASK1 */ #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 … #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT … #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 … #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT … #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 … #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT … #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 … #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT … #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 … #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT … /* Bit definitions for SMPS_POWERGOOD_MASK2 */ #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT … #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT … #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT … #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM … /* Bit definitions for SMPS_PLL_CTRL */ #define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT … #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS … #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT … #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK … /* Registers for function LDO */ #define TPS65917_LDO1_CTRL … #define TPS65917_LDO1_VOLTAGE … #define TPS65917_LDO2_CTRL … #define TPS65917_LDO2_VOLTAGE … #define TPS65917_LDO3_CTRL … #define TPS65917_LDO3_VOLTAGE … #define TPS65917_LDO4_CTRL … #define TPS65917_LDO4_VOLTAGE … #define TPS65917_LDO5_CTRL … #define TPS65917_LDO5_VOLTAGE … #define TPS65917_LDO_PD_CTRL1 … #define TPS65917_LDO_PD_CTRL2 … #define TPS65917_LDO_SHORT_STATUS1 … #define TPS65917_LDO_SHORT_STATUS2 … #define TPS65917_LDO_PD_CTRL3 … #define TPS65917_LDO_SHORT_STATUS3 … /* Bit definitions for LDO1_CTRL */ #define TPS65917_LDO1_CTRL_WR_S … #define TPS65917_LDO1_CTRL_WR_S_SHIFT … #define TPS65917_LDO1_CTRL_BYPASS_EN … #define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT … #define TPS65917_LDO1_CTRL_STATUS … #define TPS65917_LDO1_CTRL_STATUS_SHIFT … #define TPS65917_LDO1_CTRL_MODE_SLEEP … #define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_LDO1_CTRL_MODE_ACTIVE … #define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO1_VOLTAGE */ #define TPS65917_LDO1_VOLTAGE_VSEL_MASK … #define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO2_CTRL */ #define TPS65917_LDO2_CTRL_WR_S … #define TPS65917_LDO2_CTRL_WR_S_SHIFT … #define TPS65917_LDO2_CTRL_BYPASS_EN … #define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT … #define TPS65917_LDO2_CTRL_STATUS … #define TPS65917_LDO2_CTRL_STATUS_SHIFT … #define TPS65917_LDO2_CTRL_MODE_SLEEP … #define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_LDO2_CTRL_MODE_ACTIVE … #define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO2_VOLTAGE */ #define TPS65917_LDO2_VOLTAGE_VSEL_MASK … #define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO3_CTRL */ #define TPS65917_LDO3_CTRL_WR_S … #define TPS65917_LDO3_CTRL_WR_S_SHIFT … #define TPS65917_LDO3_CTRL_STATUS … #define TPS65917_LDO3_CTRL_STATUS_SHIFT … #define TPS65917_LDO3_CTRL_MODE_SLEEP … #define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_LDO3_CTRL_MODE_ACTIVE … #define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO3_VOLTAGE */ #define TPS65917_LDO3_VOLTAGE_VSEL_MASK … #define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO4_CTRL */ #define TPS65917_LDO4_CTRL_WR_S … #define TPS65917_LDO4_CTRL_WR_S_SHIFT … #define TPS65917_LDO4_CTRL_STATUS … #define TPS65917_LDO4_CTRL_STATUS_SHIFT … #define TPS65917_LDO4_CTRL_MODE_SLEEP … #define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_LDO4_CTRL_MODE_ACTIVE … #define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO4_VOLTAGE */ #define TPS65917_LDO4_VOLTAGE_VSEL_MASK … #define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO5_CTRL */ #define TPS65917_LDO5_CTRL_WR_S … #define TPS65917_LDO5_CTRL_WR_S_SHIFT … #define TPS65917_LDO5_CTRL_STATUS … #define TPS65917_LDO5_CTRL_STATUS_SHIFT … #define TPS65917_LDO5_CTRL_MODE_SLEEP … #define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_LDO5_CTRL_MODE_ACTIVE … #define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for LDO5_VOLTAGE */ #define TPS65917_LDO5_VOLTAGE_VSEL_MASK … #define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT … /* Bit definitions for LDO_PD_CTRL1 */ #define TPS65917_LDO_PD_CTRL1_LDO4 … #define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT … #define TPS65917_LDO_PD_CTRL1_LDO2 … #define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT … #define TPS65917_LDO_PD_CTRL1_LDO1 … #define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT … /* Bit definitions for LDO_PD_CTRL2 */ #define TPS65917_LDO_PD_CTRL2_LDO3 … #define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT … #define TPS65917_LDO_PD_CTRL2_LDO5 … #define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT … /* Bit definitions for LDO_PD_CTRL3 */ #define TPS65917_LDO_PD_CTRL2_LDOVANA … #define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT … /* Bit definitions for LDO_SHORT_STATUS1 */ #define TPS65917_LDO_SHORT_STATUS1_LDO4 … #define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT … #define TPS65917_LDO_SHORT_STATUS1_LDO2 … #define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT … #define TPS65917_LDO_SHORT_STATUS1_LDO1 … #define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT … /* Bit definitions for LDO_SHORT_STATUS2 */ #define TPS65917_LDO_SHORT_STATUS2_LDO3 … #define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT … #define TPS65917_LDO_SHORT_STATUS2_LDO5 … #define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT … /* Bit definitions for LDO_SHORT_STATUS2 */ #define TPS65917_LDO_SHORT_STATUS2_LDOVANA … #define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT … /* Bit definitions for REGEN1_CTRL */ #define TPS65917_REGEN1_CTRL_STATUS … #define TPS65917_REGEN1_CTRL_STATUS_SHIFT … #define TPS65917_REGEN1_CTRL_MODE_SLEEP … #define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_REGEN1_CTRL_MODE_ACTIVE … #define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for PLLEN_CTRL */ #define TPS65917_PLLEN_CTRL_STATUS … #define TPS65917_PLLEN_CTRL_STATUS_SHIFT … #define TPS65917_PLLEN_CTRL_MODE_SLEEP … #define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_PLLEN_CTRL_MODE_ACTIVE … #define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for REGEN2_CTRL */ #define TPS65917_REGEN2_CTRL_STATUS … #define TPS65917_REGEN2_CTRL_STATUS_SHIFT … #define TPS65917_REGEN2_CTRL_MODE_SLEEP … #define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_REGEN2_CTRL_MODE_ACTIVE … #define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT … /* Bit definitions for NSLEEP_RES_ASSIGN */ #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN … #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT … #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 … #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT … #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 … #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT … #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 … #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT … /* Bit definitions for NSLEEP_SMPS_ASSIGN */ #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 … #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT … #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 … #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT … #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 … #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT … #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 … #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT … #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 … #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT … /* Bit definitions for NSLEEP_LDO_ASSIGN1 */ #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 … #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT … #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 … #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT … #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 … #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT … /* Bit definitions for NSLEEP_LDO_ASSIGN2 */ #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 … #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT … #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 … #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT … /* Bit definitions for ENABLE1_RES_ASSIGN */ #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN … #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT … #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 … #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT … #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 … #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT … #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 … #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT … /* Bit definitions for ENABLE1_SMPS_ASSIGN */ #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 … #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT … #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 … #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT … #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 … #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT … #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 … #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT … #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 … #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT … /* Bit definitions for ENABLE1_LDO_ASSIGN1 */ #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 … #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT … #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 … #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT … #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 … #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT … /* Bit definitions for ENABLE1_LDO_ASSIGN2 */ #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 … #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT … #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 … #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT … /* Bit definitions for ENABLE2_RES_ASSIGN */ #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN … #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT … #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 … #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT … #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 … #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT … #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 … #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT … /* Bit definitions for ENABLE2_SMPS_ASSIGN */ #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 … #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT … #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 … #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT … #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 … #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT … #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 … #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT … #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 … #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT … /* Bit definitions for ENABLE2_LDO_ASSIGN1 */ #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 … #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT … #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 … #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT … #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 … #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT … /* Bit definitions for ENABLE2_LDO_ASSIGN2 */ #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 … #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT … #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 … #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT … /* Bit definitions for REGEN3_CTRL */ #define TPS65917_REGEN3_CTRL_STATUS … #define TPS65917_REGEN3_CTRL_STATUS_SHIFT … #define TPS65917_REGEN3_CTRL_MODE_SLEEP … #define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT … #define TPS65917_REGEN3_CTRL_MODE_ACTIVE … #define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT … /* POWERHOLD Mask field for PRIMARY_SECONDARY_PAD2 register */ #define TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK … /* Registers for function RESOURCE */ #define TPS65917_REGEN1_CTRL … #define TPS65917_PLLEN_CTRL … #define TPS65917_NSLEEP_RES_ASSIGN … #define TPS65917_NSLEEP_SMPS_ASSIGN … #define TPS65917_NSLEEP_LDO_ASSIGN1 … #define TPS65917_NSLEEP_LDO_ASSIGN2 … #define TPS65917_ENABLE1_RES_ASSIGN … #define TPS65917_ENABLE1_SMPS_ASSIGN … #define TPS65917_ENABLE1_LDO_ASSIGN1 … #define TPS65917_ENABLE1_LDO_ASSIGN2 … #define TPS65917_ENABLE2_RES_ASSIGN … #define TPS65917_ENABLE2_SMPS_ASSIGN … #define TPS65917_ENABLE2_LDO_ASSIGN1 … #define TPS65917_ENABLE2_LDO_ASSIGN2 … #define TPS65917_REGEN2_CTRL … #define TPS65917_REGEN3_CTRL … static inline int palmas_read(struct palmas *palmas, unsigned int base, unsigned int reg, unsigned int *val) { … } static inline int palmas_write(struct palmas *palmas, unsigned int base, unsigned int reg, unsigned int value) { … } static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base, unsigned int reg, const void *val, size_t val_count) { … } static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base, unsigned int reg, void *val, size_t val_count) { … } static inline int palmas_update_bits(struct palmas *palmas, unsigned int base, unsigned int reg, unsigned int mask, unsigned int val) { … } static inline int palmas_irq_get_virq(struct palmas *palmas, int irq) { … } int palmas_ext_control_req_config(struct palmas *palmas, enum palmas_external_requestor_id ext_control_req_id, int ext_ctrl, bool enable); #endif /* __LINUX_MFD_PALMAS_H */
Codebase Browser
linux