/* SPDX-License-Identifier: GPL-2.0 */ /* * Functions to access TPS6594 Power Management IC * * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/ */ #ifndef __LINUX_MFD_TPS6594_H #define __LINUX_MFD_TPS6594_H #include <linux/device.h> #include <linux/regmap.h> struct regmap_irq_chip_data; /* Chip id list */ enum pmic_id { … }; /* Macro to get page index from register address */ #define TPS6594_REG_TO_PAGE(reg) … /* Registers for page 0 */ #define TPS6594_REG_DEV_REV … #define TPS6594_REG_NVM_CODE_1 … #define TPS6594_REG_NVM_CODE_2 … #define TPS6594_REG_BUCKX_CTRL(buck_inst) … #define TPS6594_REG_BUCKX_CONF(buck_inst) … #define TPS6594_REG_BUCKX_VOUT_1(buck_inst) … #define TPS6594_REG_BUCKX_VOUT_2(buck_inst) … #define TPS6594_REG_BUCKX_PG_WINDOW(buck_inst) … #define TPS6594_REG_LDOX_CTRL(ldo_inst) … #define TPS6594_REG_LDORTC_CTRL … #define TPS6594_REG_LDOX_VOUT(ldo_inst) … #define TPS6594_REG_LDOX_PG_WINDOW(ldo_inst) … #define TPS6594_REG_VCCA_VMON_CTRL … #define TPS6594_REG_VCCA_PG_WINDOW … #define TPS6594_REG_VMON1_PG_WINDOW … #define TPS6594_REG_VMON1_PG_LEVEL … #define TPS6594_REG_VMON2_PG_WINDOW … #define TPS6594_REG_VMON2_PG_LEVEL … #define TPS6594_REG_GPIOX_CONF(gpio_inst) … #define TPS6594_REG_NPWRON_CONF … #define TPS6594_REG_GPIO_OUT_1 … #define TPS6594_REG_GPIO_OUT_2 … #define TPS6594_REG_GPIO_IN_1 … #define TPS6594_REG_GPIO_IN_2 … #define TPS6594_REG_GPIOX_OUT(gpio_inst) … #define TPS6594_REG_GPIOX_IN(gpio_inst) … #define TPS6594_REG_RAIL_SEL_1 … #define TPS6594_REG_RAIL_SEL_2 … #define TPS6594_REG_RAIL_SEL_3 … #define TPS6594_REG_FSM_TRIG_SEL_1 … #define TPS6594_REG_FSM_TRIG_SEL_2 … #define TPS6594_REG_FSM_TRIG_MASK_1 … #define TPS6594_REG_FSM_TRIG_MASK_2 … #define TPS6594_REG_FSM_TRIG_MASK_3 … #define TPS6594_REG_MASK_BUCK1_2 … #define TPS65224_REG_MASK_BUCKS … #define TPS6594_REG_MASK_BUCK3_4 … #define TPS6594_REG_MASK_BUCK5 … #define TPS6594_REG_MASK_LDO1_2 … #define TPS65224_REG_MASK_LDOS … #define TPS6594_REG_MASK_LDO3_4 … #define TPS6594_REG_MASK_VMON … #define TPS6594_REG_MASK_GPIO_FALL … #define TPS6594_REG_MASK_GPIO_RISE … #define TPS6594_REG_MASK_GPIO9_11 … #define TPS6594_REG_MASK_STARTUP … #define TPS6594_REG_MASK_MISC … #define TPS6594_REG_MASK_MODERATE_ERR … #define TPS6594_REG_MASK_FSM_ERR … #define TPS6594_REG_MASK_COMM_ERR … #define TPS6594_REG_MASK_READBACK_ERR … #define TPS6594_REG_MASK_ESM … #define TPS6594_REG_INT_TOP … #define TPS6594_REG_INT_BUCK … #define TPS6594_REG_INT_BUCK1_2 … #define TPS6594_REG_INT_BUCK3_4 … #define TPS6594_REG_INT_BUCK5 … #define TPS6594_REG_INT_LDO_VMON … #define TPS6594_REG_INT_LDO1_2 … #define TPS6594_REG_INT_LDO3_4 … #define TPS6594_REG_INT_VMON … #define TPS6594_REG_INT_GPIO … #define TPS6594_REG_INT_GPIO1_8 … #define TPS6594_REG_INT_STARTUP … #define TPS6594_REG_INT_MISC … #define TPS6594_REG_INT_MODERATE_ERR … #define TPS6594_REG_INT_SEVERE_ERR … #define TPS6594_REG_INT_FSM_ERR … #define TPS6594_REG_INT_COMM_ERR … #define TPS6594_REG_INT_READBACK_ERR … #define TPS6594_REG_INT_ESM … #define TPS6594_REG_STAT_BUCK1_2 … #define TPS6594_REG_STAT_BUCK3_4 … #define TPS6594_REG_STAT_BUCK5 … #define TPS6594_REG_STAT_LDO1_2 … #define TPS6594_REG_STAT_LDO3_4 … #define TPS6594_REG_STAT_VMON … #define TPS6594_REG_STAT_STARTUP … #define TPS6594_REG_STAT_MISC … #define TPS6594_REG_STAT_MODERATE_ERR … #define TPS6594_REG_STAT_SEVERE_ERR … #define TPS6594_REG_STAT_READBACK_ERR … #define TPS6594_REG_PGOOD_SEL_1 … #define TPS6594_REG_PGOOD_SEL_2 … #define TPS6594_REG_PGOOD_SEL_3 … #define TPS6594_REG_PGOOD_SEL_4 … #define TPS6594_REG_PLL_CTRL … #define TPS6594_REG_CONFIG_1 … #define TPS6594_REG_CONFIG_2 … #define TPS6594_REG_ENABLE_DRV_REG … #define TPS6594_REG_MISC_CTRL … #define TPS6594_REG_ENABLE_DRV_STAT … #define TPS6594_REG_RECOV_CNT_REG_1 … #define TPS6594_REG_RECOV_CNT_REG_2 … #define TPS6594_REG_FSM_I2C_TRIGGERS … #define TPS6594_REG_FSM_NSLEEP_TRIGGERS … #define TPS6594_REG_BUCK_RESET_REG … #define TPS6594_REG_SPREAD_SPECTRUM_1 … #define TPS6594_REG_FREQ_SEL … #define TPS6594_REG_FSM_STEP_SIZE … #define TPS6594_REG_LDO_RV_TIMEOUT_REG_1 … #define TPS6594_REG_LDO_RV_TIMEOUT_REG_2 … #define TPS6594_REG_USER_SPARE_REGS … #define TPS6594_REG_ESM_MCU_START_REG … #define TPS6594_REG_ESM_MCU_DELAY1_REG … #define TPS6594_REG_ESM_MCU_DELAY2_REG … #define TPS6594_REG_ESM_MCU_MODE_CFG … #define TPS6594_REG_ESM_MCU_HMAX_REG … #define TPS6594_REG_ESM_MCU_HMIN_REG … #define TPS6594_REG_ESM_MCU_LMAX_REG … #define TPS6594_REG_ESM_MCU_LMIN_REG … #define TPS6594_REG_ESM_MCU_ERR_CNT_REG … #define TPS6594_REG_ESM_SOC_START_REG … #define TPS6594_REG_ESM_SOC_DELAY1_REG … #define TPS6594_REG_ESM_SOC_DELAY2_REG … #define TPS6594_REG_ESM_SOC_MODE_CFG … #define TPS6594_REG_ESM_SOC_HMAX_REG … #define TPS6594_REG_ESM_SOC_HMIN_REG … #define TPS6594_REG_ESM_SOC_LMAX_REG … #define TPS6594_REG_ESM_SOC_LMIN_REG … #define TPS6594_REG_ESM_SOC_ERR_CNT_REG … #define TPS6594_REG_REGISTER_LOCK … #define TPS65224_REG_SRAM_ACCESS_1 … #define TPS65224_REG_SRAM_ACCESS_2 … #define TPS65224_REG_SRAM_ADDR_CTRL … #define TPS65224_REG_RECOV_CNT_PFSM_INCR … #define TPS6594_REG_MANUFACTURING_VER … #define TPS6594_REG_CUSTOMER_NVM_ID_REG … #define TPS6594_REG_VMON_CONF_REG … #define TPS6594_REG_SOFT_REBOOT_REG … #define TPS65224_REG_ADC_CTRL … #define TPS65224_REG_ADC_RESULT_REG_1 … #define TPS65224_REG_ADC_RESULT_REG_2 … #define TPS6594_REG_RTC_SECONDS … #define TPS6594_REG_RTC_MINUTES … #define TPS6594_REG_RTC_HOURS … #define TPS6594_REG_RTC_DAYS … #define TPS6594_REG_RTC_MONTHS … #define TPS6594_REG_RTC_YEARS … #define TPS6594_REG_RTC_WEEKS … #define TPS6594_REG_ALARM_SECONDS … #define TPS6594_REG_ALARM_MINUTES … #define TPS6594_REG_ALARM_HOURS … #define TPS6594_REG_ALARM_DAYS … #define TPS6594_REG_ALARM_MONTHS … #define TPS6594_REG_ALARM_YEARS … #define TPS6594_REG_RTC_CTRL_1 … #define TPS6594_REG_RTC_CTRL_2 … #define TPS65224_REG_STARTUP_CTRL … #define TPS6594_REG_RTC_STATUS … #define TPS6594_REG_RTC_INTERRUPTS … #define TPS6594_REG_RTC_COMP_LSB … #define TPS6594_REG_RTC_COMP_MSB … #define TPS6594_REG_RTC_RESET_STATUS … #define TPS6594_REG_SCRATCH_PAD_REG_1 … #define TPS6594_REG_SCRATCH_PAD_REG_2 … #define TPS6594_REG_SCRATCH_PAD_REG_3 … #define TPS6594_REG_SCRATCH_PAD_REG_4 … #define TPS6594_REG_PFSM_DELAY_REG_1 … #define TPS6594_REG_PFSM_DELAY_REG_2 … #define TPS6594_REG_PFSM_DELAY_REG_3 … #define TPS6594_REG_PFSM_DELAY_REG_4 … #define TPS65224_REG_ADC_GAIN_COMP_REG … #define TPS65224_REG_CRC_CALC_CONTROL … #define TPS65224_REG_REGMAP_USER_CRC_LOW … #define TPS65224_REG_REGMAP_USER_CRC_HIGH … /* Registers for page 1 */ #define TPS6594_REG_SERIAL_IF_CONFIG … #define TPS6594_REG_I2C1_ID … #define TPS6594_REG_I2C2_ID … /* Registers for page 4 */ #define TPS6594_REG_WD_ANSWER_REG … #define TPS6594_REG_WD_QUESTION_ANSW_CNT … #define TPS6594_REG_WD_WIN1_CFG … #define TPS6594_REG_WD_WIN2_CFG … #define TPS6594_REG_WD_LONGWIN_CFG … #define TPS6594_REG_WD_MODE_REG … #define TPS6594_REG_WD_QA_CFG … #define TPS6594_REG_WD_ERR_STATUS … #define TPS6594_REG_WD_THR_CFG … #define TPS6594_REG_DWD_FAIL_CNT_REG … /* BUCKX_CTRL register field definition */ #define TPS6594_BIT_BUCK_EN … #define TPS6594_BIT_BUCK_FPWM … #define TPS6594_BIT_BUCK_FPWM_MP … #define TPS6594_BIT_BUCK_VSEL … #define TPS6594_BIT_BUCK_VMON_EN … #define TPS6594_BIT_BUCK_PLDN … #define TPS6594_BIT_BUCK_RV_SEL … /* TPS6594 BUCKX_CONF register field definition */ #define TPS6594_MASK_BUCK_SLEW_RATE … #define TPS6594_MASK_BUCK_ILIM … /* TPS65224 BUCKX_CONF register field definition */ #define TPS65224_MASK_BUCK_SLEW_RATE … /* TPS6594 BUCKX_PG_WINDOW register field definition */ #define TPS6594_MASK_BUCK_OV_THR … #define TPS6594_MASK_BUCK_UV_THR … /* TPS65224 BUCKX_PG_WINDOW register field definition */ #define TPS65224_MASK_BUCK_VMON_THR … /* TPS6594 BUCKX_VOUT register field definition */ #define TPS6594_MASK_BUCKS_VSET … /* TPS65224 BUCKX_VOUT register field definition */ #define TPS65224_MASK_BUCK1_VSET … #define TPS65224_MASK_BUCKS_VSET … /* LDOX_CTRL register field definition */ #define TPS6594_BIT_LDO_EN … #define TPS6594_BIT_LDO_SLOW_RAMP … #define TPS6594_BIT_LDO_VMON_EN … #define TPS6594_MASK_LDO_PLDN … #define TPS6594_BIT_LDO_RV_SEL … #define TPS65224_BIT_LDO_DISCHARGE_EN … /* LDORTC_CTRL register field definition */ #define TPS6594_BIT_LDORTC_DIS … /* LDOX_VOUT register field definition */ #define TPS6594_MASK_LDO123_VSET … #define TPS6594_MASK_LDO4_VSET … #define TPS6594_BIT_LDO_BYPASS … /* LDOX_PG_WINDOW register field definition */ #define TPS6594_MASK_LDO_OV_THR … #define TPS6594_MASK_LDO_UV_THR … /* LDOX_PG_WINDOW register field definition */ #define TPS65224_MASK_LDO_VMON_THR … /* VCCA_VMON_CTRL register field definition */ #define TPS6594_BIT_VMON_EN … #define TPS6594_BIT_VMON1_EN … #define TPS6594_BIT_VMON1_RV_SEL … #define TPS6594_BIT_VMON2_EN … #define TPS6594_BIT_VMON2_RV_SEL … #define TPS6594_BIT_VMON_DEGLITCH_SEL … #define TPS65224_BIT_VMON_DEGLITCH_SEL … /* VCCA_PG_WINDOW register field definition */ #define TPS6594_MASK_VCCA_OV_THR … #define TPS6594_MASK_VCCA_UV_THR … #define TPS65224_MASK_VCCA_VMON_THR … #define TPS6594_BIT_VCCA_PG_SET … /* VMONX_PG_WINDOW register field definition */ #define TPS6594_MASK_VMONX_OV_THR … #define TPS6594_MASK_VMONX_UV_THR … #define TPS6594_BIT_VMONX_RANGE … /* VMONX_PG_WINDOW register field definition */ #define TPS65224_MASK_VMONX_THR … /* GPIOX_CONF register field definition */ #define TPS6594_BIT_GPIO_DIR … #define TPS6594_BIT_GPIO_OD … #define TPS6594_BIT_GPIO_PU_SEL … #define TPS6594_BIT_GPIO_PU_PD_EN … #define TPS6594_BIT_GPIO_DEGLITCH_EN … #define TPS6594_MASK_GPIO_SEL … #define TPS65224_MASK_GPIO_SEL … #define TPS65224_MASK_GPIO_SEL_GPIO6 … /* NPWRON_CONF register field definition */ #define TPS6594_BIT_NRSTOUT_OD … #define TPS6594_BIT_ENABLE_PU_SEL … #define TPS6594_BIT_ENABLE_PU_PD_EN … #define TPS6594_BIT_ENABLE_DEGLITCH_EN … #define TPS6594_BIT_ENABLE_POL … #define TPS6594_MASK_NPWRON_SEL … /* POWER_ON_CONFIG register field definition */ #define TPS65224_BIT_NINT_ENDRV_PU_SEL … #define TPS65224_BIT_NINT_ENDRV_SEL … #define TPS65224_BIT_EN_PB_DEGL … #define TPS65224_MASK_EN_PB_VSENSE_CONFIG … /* GPIO_OUT_X register field definition */ #define TPS6594_BIT_GPIOX_OUT(gpio_inst) … /* GPIO_IN_X register field definition */ #define TPS6594_BIT_GPIOX_IN(gpio_inst) … #define TPS6594_BIT_NPWRON_IN … /* GPIO_OUT_X register field definition */ #define TPS65224_BIT_GPIOX_OUT(gpio_inst) … /* GPIO_IN_X register field definition */ #define TPS65224_BIT_GPIOX_IN(gpio_inst) … /* RAIL_SEL_1 register field definition */ #define TPS6594_MASK_BUCK1_GRP_SEL … #define TPS6594_MASK_BUCK2_GRP_SEL … #define TPS6594_MASK_BUCK3_GRP_SEL … #define TPS6594_MASK_BUCK4_GRP_SEL … /* RAIL_SEL_2 register field definition */ #define TPS6594_MASK_BUCK5_GRP_SEL … #define TPS6594_MASK_LDO1_GRP_SEL … #define TPS6594_MASK_LDO2_GRP_SEL … #define TPS6594_MASK_LDO3_GRP_SEL … /* RAIL_SEL_3 register field definition */ #define TPS6594_MASK_LDO4_GRP_SEL … #define TPS6594_MASK_VCCA_GRP_SEL … #define TPS6594_MASK_VMON1_GRP_SEL … #define TPS6594_MASK_VMON2_GRP_SEL … /* FSM_TRIG_SEL_1 register field definition */ #define TPS6594_MASK_MCU_RAIL_TRIG … #define TPS6594_MASK_SOC_RAIL_TRIG … #define TPS6594_MASK_OTHER_RAIL_TRIG … #define TPS6594_MASK_SEVERE_ERR_TRIG … /* FSM_TRIG_SEL_2 register field definition */ #define TPS6594_MASK_MODERATE_ERR_TRIG … /* FSM_TRIG_MASK_X register field definition */ #define TPS6594_BIT_GPIOX_FSM_MASK(gpio_inst) … #define TPS6594_BIT_GPIOX_FSM_MASK_POL(gpio_inst) … #define TPS65224_BIT_GPIOX_FSM_MASK(gpio_inst) … #define TPS65224_BIT_GPIOX_FSM_MASK_POL(gpio_inst) … /* MASK_BUCKX register field definition */ #define TPS6594_BIT_BUCKX_OV_MASK(buck_inst) … #define TPS6594_BIT_BUCKX_UV_MASK(buck_inst) … #define TPS6594_BIT_BUCKX_ILIM_MASK(buck_inst) … /* MASK_LDOX register field definition */ #define TPS6594_BIT_LDOX_OV_MASK(ldo_inst) … #define TPS6594_BIT_LDOX_UV_MASK(ldo_inst) … #define TPS6594_BIT_LDOX_ILIM_MASK(ldo_inst) … /* MASK_VMON register field definition */ #define TPS6594_BIT_VCCA_OV_MASK … #define TPS6594_BIT_VCCA_UV_MASK … #define TPS6594_BIT_VMON1_OV_MASK … #define TPS6594_BIT_VMON1_UV_MASK … #define TPS6594_BIT_VMON2_OV_MASK … #define TPS6594_BIT_VMON2_UV_MASK … /* MASK_BUCK Register field definition */ #define TPS65224_BIT_BUCK1_UVOV_MASK … #define TPS65224_BIT_BUCK2_UVOV_MASK … #define TPS65224_BIT_BUCK3_UVOV_MASK … #define TPS65224_BIT_BUCK4_UVOV_MASK … /* MASK_LDO_VMON register field definition */ #define TPS65224_BIT_LDO1_UVOV_MASK … #define TPS65224_BIT_LDO2_UVOV_MASK … #define TPS65224_BIT_LDO3_UVOV_MASK … #define TPS65224_BIT_VCCA_UVOV_MASK … #define TPS65224_BIT_VMON1_UVOV_MASK … #define TPS65224_BIT_VMON2_UVOV_MASK … /* MASK_GPIOX register field definition */ #define TPS6594_BIT_GPIOX_FALL_MASK(gpio_inst) … #define TPS6594_BIT_GPIOX_RISE_MASK(gpio_inst) … /* MASK_GPIOX register field definition */ #define TPS65224_BIT_GPIOX_FALL_MASK(gpio_inst) … #define TPS65224_BIT_GPIOX_RISE_MASK(gpio_inst) … /* MASK_STARTUP register field definition */ #define TPS6594_BIT_NPWRON_START_MASK … #define TPS6594_BIT_ENABLE_MASK … #define TPS6594_BIT_FSD_MASK … #define TPS6594_BIT_SOFT_REBOOT_MASK … #define TPS65224_BIT_VSENSE_MASK … #define TPS65224_BIT_PB_SHORT_MASK … /* MASK_MISC register field definition */ #define TPS6594_BIT_BIST_PASS_MASK … #define TPS6594_BIT_EXT_CLK_MASK … #define TPS65224_BIT_REG_UNLOCK_MASK … #define TPS6594_BIT_TWARN_MASK … #define TPS65224_BIT_PB_LONG_MASK … #define TPS65224_BIT_PB_FALL_MASK … #define TPS65224_BIT_PB_RISE_MASK … #define TPS65224_BIT_ADC_CONV_READY_MASK … /* MASK_MODERATE_ERR register field definition */ #define TPS6594_BIT_BIST_FAIL_MASK … #define TPS6594_BIT_REG_CRC_ERR_MASK … #define TPS6594_BIT_SPMI_ERR_MASK … #define TPS6594_BIT_NPWRON_LONG_MASK … #define TPS6594_BIT_NINT_READBACK_MASK … #define TPS6594_BIT_NRSTOUT_READBACK_MASK … /* MASK_FSM_ERR register field definition */ #define TPS6594_BIT_IMM_SHUTDOWN_MASK … #define TPS6594_BIT_ORD_SHUTDOWN_MASK … #define TPS6594_BIT_MCU_PWR_ERR_MASK … #define TPS6594_BIT_SOC_PWR_ERR_MASK … #define TPS65224_BIT_COMM_ERR_MASK … #define TPS65224_BIT_I2C2_ERR_MASK … /* MASK_COMM_ERR register field definition */ #define TPS6594_BIT_COMM_FRM_ERR_MASK … #define TPS6594_BIT_COMM_CRC_ERR_MASK … #define TPS6594_BIT_COMM_ADR_ERR_MASK … #define TPS6594_BIT_I2C2_CRC_ERR_MASK … #define TPS6594_BIT_I2C2_ADR_ERR_MASK … /* MASK_READBACK_ERR register field definition */ #define TPS6594_BIT_EN_DRV_READBACK_MASK … #define TPS6594_BIT_NRSTOUT_SOC_READBACK_MASK … /* MASK_ESM register field definition */ #define TPS6594_BIT_ESM_SOC_PIN_MASK … #define TPS6594_BIT_ESM_SOC_FAIL_MASK … #define TPS6594_BIT_ESM_SOC_RST_MASK … #define TPS6594_BIT_ESM_MCU_PIN_MASK … #define TPS6594_BIT_ESM_MCU_FAIL_MASK … #define TPS6594_BIT_ESM_MCU_RST_MASK … /* INT_TOP register field definition */ #define TPS6594_BIT_BUCK_INT … #define TPS6594_BIT_LDO_VMON_INT … #define TPS6594_BIT_GPIO_INT … #define TPS6594_BIT_STARTUP_INT … #define TPS6594_BIT_MISC_INT … #define TPS6594_BIT_MODERATE_ERR_INT … #define TPS6594_BIT_SEVERE_ERR_INT … #define TPS6594_BIT_FSM_ERR_INT … /* INT_BUCK register field definition */ #define TPS6594_BIT_BUCK1_2_INT … #define TPS6594_BIT_BUCK3_4_INT … #define TPS6594_BIT_BUCK5_INT … /* INT_BUCK register field definition */ #define TPS65224_BIT_BUCK1_UVOV_INT … #define TPS65224_BIT_BUCK2_UVOV_INT … #define TPS65224_BIT_BUCK3_UVOV_INT … #define TPS65224_BIT_BUCK4_UVOV_INT … /* INT_BUCKX register field definition */ #define TPS6594_BIT_BUCKX_OV_INT(buck_inst) … #define TPS6594_BIT_BUCKX_UV_INT(buck_inst) … #define TPS6594_BIT_BUCKX_SC_INT(buck_inst) … #define TPS6594_BIT_BUCKX_ILIM_INT(buck_inst) … /* INT_LDO_VMON register field definition */ #define TPS6594_BIT_LDO1_2_INT … #define TPS6594_BIT_LDO3_4_INT … #define TPS6594_BIT_VCCA_INT … /* INT_LDO_VMON register field definition */ #define TPS65224_BIT_LDO1_UVOV_INT … #define TPS65224_BIT_LDO2_UVOV_INT … #define TPS65224_BIT_LDO3_UVOV_INT … #define TPS65224_BIT_VCCA_UVOV_INT … #define TPS65224_BIT_VMON1_UVOV_INT … #define TPS65224_BIT_VMON2_UVOV_INT … /* INT_LDOX register field definition */ #define TPS6594_BIT_LDOX_OV_INT(ldo_inst) … #define TPS6594_BIT_LDOX_UV_INT(ldo_inst) … #define TPS6594_BIT_LDOX_SC_INT(ldo_inst) … #define TPS6594_BIT_LDOX_ILIM_INT(ldo_inst) … /* INT_VMON register field definition */ #define TPS6594_BIT_VCCA_OV_INT … #define TPS6594_BIT_VCCA_UV_INT … #define TPS6594_BIT_VMON1_OV_INT … #define TPS6594_BIT_VMON1_UV_INT … #define TPS6594_BIT_VMON1_RV_INT … #define TPS6594_BIT_VMON2_OV_INT … #define TPS6594_BIT_VMON2_UV_INT … #define TPS6594_BIT_VMON2_RV_INT … /* INT_GPIO register field definition */ #define TPS6594_BIT_GPIO9_INT … #define TPS6594_BIT_GPIO10_INT … #define TPS6594_BIT_GPIO11_INT … #define TPS6594_BIT_GPIO1_8_INT … /* INT_GPIOX register field definition */ #define TPS6594_BIT_GPIOX_INT(gpio_inst) … /* INT_GPIO register field definition */ #define TPS65224_BIT_GPIO1_INT … #define TPS65224_BIT_GPIO2_INT … #define TPS65224_BIT_GPIO3_INT … #define TPS65224_BIT_GPIO4_INT … #define TPS65224_BIT_GPIO5_INT … #define TPS65224_BIT_GPIO6_INT … /* INT_STARTUP register field definition */ #define TPS6594_BIT_NPWRON_START_INT … #define TPS65224_BIT_VSENSE_INT … #define TPS6594_BIT_ENABLE_INT … #define TPS6594_BIT_RTC_INT … #define TPS65224_BIT_PB_SHORT_INT … #define TPS6594_BIT_FSD_INT … #define TPS6594_BIT_SOFT_REBOOT_INT … /* INT_MISC register field definition */ #define TPS6594_BIT_BIST_PASS_INT … #define TPS6594_BIT_EXT_CLK_INT … #define TPS65224_BIT_REG_UNLOCK_INT … #define TPS6594_BIT_TWARN_INT … #define TPS65224_BIT_PB_LONG_INT … #define TPS65224_BIT_PB_FALL_INT … #define TPS65224_BIT_PB_RISE_INT … #define TPS65224_BIT_ADC_CONV_READY_INT … /* INT_MODERATE_ERR register field definition */ #define TPS6594_BIT_TSD_ORD_INT … #define TPS6594_BIT_BIST_FAIL_INT … #define TPS6594_BIT_REG_CRC_ERR_INT … #define TPS6594_BIT_RECOV_CNT_INT … #define TPS6594_BIT_SPMI_ERR_INT … #define TPS6594_BIT_NPWRON_LONG_INT … #define TPS6594_BIT_NINT_READBACK_INT … #define TPS6594_BIT_NRSTOUT_READBACK_INT … /* INT_SEVERE_ERR register field definition */ #define TPS6594_BIT_TSD_IMM_INT … #define TPS6594_BIT_VCCA_OVP_INT … #define TPS6594_BIT_PFSM_ERR_INT … #define TPS65224_BIT_BG_XMON_INT … /* INT_FSM_ERR register field definition */ #define TPS6594_BIT_IMM_SHUTDOWN_INT … #define TPS6594_BIT_ORD_SHUTDOWN_INT … #define TPS6594_BIT_MCU_PWR_ERR_INT … #define TPS6594_BIT_SOC_PWR_ERR_INT … #define TPS6594_BIT_COMM_ERR_INT … #define TPS6594_BIT_READBACK_ERR_INT … #define TPS65224_BIT_I2C2_ERR_INT … #define TPS6594_BIT_ESM_INT … #define TPS6594_BIT_WD_INT … /* INT_COMM_ERR register field definition */ #define TPS6594_BIT_COMM_FRM_ERR_INT … #define TPS6594_BIT_COMM_CRC_ERR_INT … #define TPS6594_BIT_COMM_ADR_ERR_INT … #define TPS6594_BIT_I2C2_CRC_ERR_INT … #define TPS6594_BIT_I2C2_ADR_ERR_INT … /* INT_READBACK_ERR register field definition */ #define TPS6594_BIT_EN_DRV_READBACK_INT … #define TPS6594_BIT_NRSTOUT_SOC_READBACK_INT … /* INT_ESM register field definition */ #define TPS6594_BIT_ESM_SOC_PIN_INT … #define TPS6594_BIT_ESM_SOC_FAIL_INT … #define TPS6594_BIT_ESM_SOC_RST_INT … #define TPS6594_BIT_ESM_MCU_PIN_INT … #define TPS6594_BIT_ESM_MCU_FAIL_INT … #define TPS6594_BIT_ESM_MCU_RST_INT … /* STAT_BUCKX register field definition */ #define TPS6594_BIT_BUCKX_OV_STAT(buck_inst) … #define TPS6594_BIT_BUCKX_UV_STAT(buck_inst) … #define TPS6594_BIT_BUCKX_ILIM_STAT(buck_inst) … /* STAT_LDOX register field definition */ #define TPS6594_BIT_LDOX_OV_STAT(ldo_inst) … #define TPS6594_BIT_LDOX_UV_STAT(ldo_inst) … #define TPS6594_BIT_LDOX_ILIM_STAT(ldo_inst) … /* STAT_VMON register field definition */ #define TPS6594_BIT_VCCA_OV_STAT … #define TPS6594_BIT_VCCA_UV_STAT … #define TPS6594_BIT_VMON1_OV_STAT … #define TPS6594_BIT_VMON1_UV_STAT … #define TPS6594_BIT_VMON2_OV_STAT … #define TPS6594_BIT_VMON2_UV_STAT … /* STAT_LDO_VMON register field definition */ #define TPS65224_BIT_LDO1_UVOV_STAT … #define TPS65224_BIT_LDO2_UVOV_STAT … #define TPS65224_BIT_LDO3_UVOV_STAT … #define TPS65224_BIT_VCCA_UVOV_STAT … #define TPS65224_BIT_VMON1_UVOV_STAT … #define TPS65224_BIT_VMON2_UVOV_STAT … /* STAT_STARTUP register field definition */ #define TPS65224_BIT_VSENSE_STAT … #define TPS6594_BIT_ENABLE_STAT … #define TPS65224_BIT_PB_LEVEL_STAT … /* STAT_MISC register field definition */ #define TPS6594_BIT_EXT_CLK_STAT … #define TPS6594_BIT_TWARN_STAT … /* STAT_MODERATE_ERR register field definition */ #define TPS6594_BIT_TSD_ORD_STAT … /* STAT_SEVERE_ERR register field definition */ #define TPS6594_BIT_TSD_IMM_STAT … #define TPS6594_BIT_VCCA_OVP_STAT … #define TPS65224_BIT_BG_XMON_STAT … /* STAT_READBACK_ERR register field definition */ #define TPS6594_BIT_EN_DRV_READBACK_STAT … #define TPS6594_BIT_NINT_READBACK_STAT … #define TPS6594_BIT_NRSTOUT_READBACK_STAT … #define TPS6594_BIT_NRSTOUT_SOC_READBACK_STAT … /* PGOOD_SEL_1 register field definition */ #define TPS6594_MASK_PGOOD_SEL_BUCK1 … #define TPS6594_MASK_PGOOD_SEL_BUCK2 … #define TPS6594_MASK_PGOOD_SEL_BUCK3 … #define TPS6594_MASK_PGOOD_SEL_BUCK4 … /* PGOOD_SEL_2 register field definition */ #define TPS6594_MASK_PGOOD_SEL_BUCK5 … /* PGOOD_SEL_3 register field definition */ #define TPS6594_MASK_PGOOD_SEL_LDO1 … #define TPS6594_MASK_PGOOD_SEL_LDO2 … #define TPS6594_MASK_PGOOD_SEL_LDO3 … #define TPS6594_MASK_PGOOD_SEL_LDO4 … /* PGOOD_SEL_4 register field definition */ #define TPS6594_BIT_PGOOD_SEL_VCCA … #define TPS6594_BIT_PGOOD_SEL_VMON1 … #define TPS6594_BIT_PGOOD_SEL_VMON2 … #define TPS6594_BIT_PGOOD_SEL_TDIE_WARN … #define TPS6594_BIT_PGOOD_SEL_NRSTOUT … #define TPS6594_BIT_PGOOD_SEL_NRSTOUT_SOC … #define TPS6594_BIT_PGOOD_POL … #define TPS6594_BIT_PGOOD_WINDOW … /* PLL_CTRL register field definition */ #define TPS6594_MASK_EXT_CLK_FREQ … /* CONFIG_1 register field definition */ #define TPS6594_BIT_TWARN_LEVEL … #define TPS6594_BIT_TSD_ORD_LEVEL … #define TPS6594_BIT_I2C1_HS … #define TPS6594_BIT_I2C2_HS … #define TPS6594_BIT_EN_ILIM_FSM_CTRL … #define TPS6594_BIT_NSLEEP1_MASK … #define TPS6594_BIT_NSLEEP2_MASK … /* CONFIG_2 register field definition */ #define TPS6594_BIT_BB_CHARGER_EN … #define TPS6594_BIT_BB_ICHR … #define TPS6594_MASK_BB_VEOC … #define TPS65224_BIT_I2C1_SPI_CRC_EN … #define TPS65224_BIT_I2C2_CRC_EN … #define TPS6594_BB_EOC_RDY … /* ENABLE_DRV_REG register field definition */ #define TPS6594_BIT_ENABLE_DRV … /* MISC_CTRL register field definition */ #define TPS6594_BIT_NRSTOUT … #define TPS6594_BIT_NRSTOUT_SOC … #define TPS6594_BIT_LPM_EN … #define TPS6594_BIT_CLKMON_EN … #define TPS6594_BIT_AMUXOUT_EN … #define TPS6594_BIT_SEL_EXT_CLK … #define TPS6594_MASK_SYNCCLKOUT_FREQ_SEL … /* ENABLE_DRV_STAT register field definition */ #define TPS6594_BIT_EN_DRV_IN … #define TPS6594_BIT_NRSTOUT_IN … #define TPS6594_BIT_NRSTOUT_SOC_IN … #define TPS6594_BIT_FORCE_EN_DRV_LOW … #define TPS6594_BIT_SPMI_LPM_EN … #define TPS65224_BIT_TSD_DISABLE … /* RECOV_CNT_REG_1 register field definition */ #define TPS6594_MASK_RECOV_CNT … /* RECOV_CNT_REG_2 register field definition */ #define TPS6594_MASK_RECOV_CNT_THR … #define TPS6594_BIT_RECOV_CNT_CLR … /* FSM_I2C_TRIGGERS register field definition */ #define TPS6594_BIT_TRIGGER_I2C(bit) … /* FSM_NSLEEP_TRIGGERS register field definition */ #define TPS6594_BIT_NSLEEP1B … #define TPS6594_BIT_NSLEEP2B … /* BUCK_RESET_REG register field definition */ #define TPS6594_BIT_BUCKX_RESET(buck_inst) … /* SPREAD_SPECTRUM_1 register field definition */ #define TPS6594_MASK_SS_DEPTH … #define TPS6594_BIT_SS_EN … /* FREQ_SEL register field definition */ #define TPS6594_BIT_BUCKX_FREQ_SEL(buck_inst) … /* FSM_STEP_SIZE register field definition */ #define TPS6594_MASK_PFSM_DELAY_STEP … /* LDO_RV_TIMEOUT_REG_1 register field definition */ #define TPS6594_MASK_LDO1_RV_TIMEOUT … #define TPS6594_MASK_LDO2_RV_TIMEOUT … /* LDO_RV_TIMEOUT_REG_2 register field definition */ #define TPS6594_MASK_LDO3_RV_TIMEOUT … #define TPS6594_MASK_LDO4_RV_TIMEOUT … /* USER_SPARE_REGS register field definition */ #define TPS6594_BIT_USER_SPARE(bit) … /* ESM_MCU_START_REG register field definition */ #define TPS6594_BIT_ESM_MCU_START … /* ESM_MCU_MODE_CFG register field definition */ #define TPS6594_MASK_ESM_MCU_ERR_CNT_TH … #define TPS6594_BIT_ESM_MCU_ENDRV … #define TPS6594_BIT_ESM_MCU_EN … #define TPS6594_BIT_ESM_MCU_MODE … /* ESM_MCU_ERR_CNT_REG register field definition */ #define TPS6594_MASK_ESM_MCU_ERR_CNT … /* ESM_SOC_START_REG register field definition */ #define TPS6594_BIT_ESM_SOC_START … /* ESM_MCU_START_REG register field definition */ #define TPS65224_BIT_ESM_MCU_START … /* ESM_SOC_MODE_CFG register field definition */ #define TPS6594_MASK_ESM_SOC_ERR_CNT_TH … #define TPS6594_BIT_ESM_SOC_ENDRV … #define TPS6594_BIT_ESM_SOC_EN … #define TPS6594_BIT_ESM_SOC_MODE … /* ESM_MCU_MODE_CFG register field definition */ #define TPS65224_MASK_ESM_MCU_ERR_CNT_TH … #define TPS65224_BIT_ESM_MCU_ENDRV … #define TPS65224_BIT_ESM_MCU_EN … #define TPS65224_BIT_ESM_MCU_MODE … /* ESM_SOC_ERR_CNT_REG register field definition */ #define TPS6594_MASK_ESM_SOC_ERR_CNT … /* ESM_MCU_ERR_CNT_REG register field definition */ #define TPS6594_MASK_ESM_MCU_ERR_CNT … /* REGISTER_LOCK register field definition */ #define TPS6594_BIT_REGISTER_LOCK_STATUS … /* VMON_CONF register field definition */ #define TPS6594_MASK_VMON1_SLEW_RATE … #define TPS6594_MASK_VMON2_SLEW_RATE … /* SRAM_ACCESS_1 Register field definition */ #define TPS65224_MASk_SRAM_UNLOCK_SEQ … /* SRAM_ACCESS_2 Register field definition */ #define TPS65224_BIT_SRAM_WRITE_MODE … #define TPS65224_BIT_OTP_PROG_USER … #define TPS65224_BIT_OTP_PROG_PFSM … #define TPS65224_BIT_OTP_PROG_STATUS … #define TPS65224_BIT_SRAM_UNLOCKED … #define TPS65224_USER_PROG_ALLOWED … /* SRAM_ADDR_CTRL Register field definition */ #define TPS65224_MASk_SRAM_SEL … /* RECOV_CNT_PFSM_INCR Register field definition */ #define TPS65224_BIT_INCREMENT_RECOV_CNT … /* MANUFACTURING_VER Register field definition */ #define TPS65224_MASK_SILICON_REV … /* CUSTOMER_NVM_ID_REG Register field definition */ #define TPS65224_MASK_CUSTOMER_NVM_ID … /* SOFT_REBOOT_REG register field definition */ #define TPS6594_BIT_SOFT_REBOOT … /* RTC_SECONDS & ALARM_SECONDS register field definition */ #define TPS6594_MASK_SECOND_0 … #define TPS6594_MASK_SECOND_1 … /* RTC_MINUTES & ALARM_MINUTES register field definition */ #define TPS6594_MASK_MINUTE_0 … #define TPS6594_MASK_MINUTE_1 … /* RTC_HOURS & ALARM_HOURS register field definition */ #define TPS6594_MASK_HOUR_0 … #define TPS6594_MASK_HOUR_1 … #define TPS6594_BIT_PM_NAM … /* RTC_DAYS & ALARM_DAYS register field definition */ #define TPS6594_MASK_DAY_0 … #define TPS6594_MASK_DAY_1 … /* RTC_MONTHS & ALARM_MONTHS register field definition */ #define TPS6594_MASK_MONTH_0 … #define TPS6594_BIT_MONTH_1 … /* RTC_YEARS & ALARM_YEARS register field definition */ #define TPS6594_MASK_YEAR_0 … #define TPS6594_MASK_YEAR_1 … /* RTC_WEEKS register field definition */ #define TPS6594_MASK_WEEK … /* RTC_CTRL_1 register field definition */ #define TPS6594_BIT_STOP_RTC … #define TPS6594_BIT_ROUND_30S … #define TPS6594_BIT_AUTO_COMP … #define TPS6594_BIT_MODE_12_24 … #define TPS6594_BIT_SET_32_COUNTER … #define TPS6594_BIT_GET_TIME … #define TPS6594_BIT_RTC_V_OPT … /* RTC_CTRL_2 register field definition */ #define TPS6594_BIT_XTAL_EN … #define TPS6594_MASK_XTAL_SEL … #define TPS6594_BIT_LP_STANDBY_SEL … #define TPS6594_BIT_FAST_BIST … #define TPS6594_MASK_STARTUP_DEST … #define TPS6594_BIT_FIRST_STARTUP_DONE … /* RTC_STATUS register field definition */ #define TPS6594_BIT_RUN … #define TPS6594_BIT_TIMER … #define TPS6594_BIT_ALARM … #define TPS6594_BIT_POWER_UP … /* RTC_INTERRUPTS register field definition */ #define TPS6594_MASK_EVERY … #define TPS6594_BIT_IT_TIMER … #define TPS6594_BIT_IT_ALARM … /* RTC_RESET_STATUS register field definition */ #define TPS6594_BIT_RESET_STATUS_RTC … /* SERIAL_IF_CONFIG register field definition */ #define TPS6594_BIT_I2C_SPI_SEL … #define TPS6594_BIT_I2C1_SPI_CRC_EN … #define TPS6594_BIT_I2C2_CRC_EN … #define TPS6594_MASK_T_CRC … /* ADC_CTRL Register field definition */ #define TPS65224_BIT_ADC_START … #define TPS65224_BIT_ADC_CONT_CONV … #define TPS65224_BIT_ADC_THERMAL_SEL … #define TPS65224_BIT_ADC_RDIV_EN … #define TPS65224_BIT_ADC_STATUS … /* ADC_RESULT_REG_1 Register field definition */ #define TPS65224_MASK_ADC_RESULT_11_4 … /* ADC_RESULT_REG_2 Register field definition */ #define TPS65224_MASK_ADC_RESULT_3_0 … /* STARTUP_CTRL Register field definition */ #define TPS65224_MASK_STARTUP_DEST … #define TPS65224_BIT_FIRST_STARTUP_DONE … /* SCRATCH_PAD_REG_1 Register field definition */ #define TPS6594_MASK_SCRATCH_PAD_1 … /* SCRATCH_PAD_REG_2 Register field definition */ #define TPS6594_MASK_SCRATCH_PAD_2 … /* SCRATCH_PAD_REG_3 Register field definition */ #define TPS6594_MASK_SCRATCH_PAD_3 … /* SCRATCH_PAD_REG_4 Register field definition */ #define TPS6594_MASK_SCRATCH_PAD_4 … /* PFSM_DELAY_REG_1 Register field definition */ #define TPS6594_MASK_PFSM_DELAY1 … /* PFSM_DELAY_REG_2 Register field definition */ #define TPS6594_MASK_PFSM_DELAY2 … /* PFSM_DELAY_REG_3 Register field definition */ #define TPS6594_MASK_PFSM_DELAY3 … /* PFSM_DELAY_REG_4 Register field definition */ #define TPS6594_MASK_PFSM_DELAY4 … /* CRC_CALC_CONTROL Register field definition */ #define TPS65224_BIT_RUN_CRC_BIST … #define TPS65224_BIT_RUN_CRC_UPDATE … /* ADC_GAIN_COMP_REG Register field definition */ #define TPS65224_MASK_ADC_GAIN_COMP … /* REGMAP_USER_CRC_LOW Register field definition */ #define TPS65224_MASK_REGMAP_USER_CRC16_LOW … /* REGMAP_USER_CRC_HIGH Register field definition */ #define TPS65224_MASK_REGMAP_USER_CRC16_HIGH … /* WD_ANSWER_REG Register field definition */ #define TPS6594_MASK_WD_ANSWER … /* WD_QUESTION_ANSW_CNT register field definition */ #define TPS6594_MASK_WD_QUESTION … #define TPS6594_MASK_WD_ANSW_CNT … #define TPS65224_BIT_INT_TOP_STATUS … /* WD WIN1_CFG register field definition */ #define TPS6594_MASK_WD_WIN1_CFG … /* WD WIN2_CFG register field definition */ #define TPS6594_MASK_WD_WIN2_CFG … /* WD LongWin register field definition */ #define TPS6594_MASK_WD_LONGWIN_CFG … /* WD_MODE_REG register field definition */ #define TPS6594_BIT_WD_RETURN_LONGWIN … #define TPS6594_BIT_WD_MODE_SELECT … #define TPS6594_BIT_WD_PWRHOLD … #define TPS65224_BIT_WD_ENDRV_SEL … #define TPS65224_BIT_WD_CNT_SEL … /* WD_QA_CFG register field definition */ #define TPS6594_MASK_WD_QUESTION_SEED … #define TPS6594_MASK_WD_QA_LFSR … #define TPS6594_MASK_WD_QA_FDBK … /* WD_ERR_STATUS register field definition */ #define TPS6594_BIT_WD_LONGWIN_TIMEOUT_INT … #define TPS6594_BIT_WD_TIMEOUT … #define TPS6594_BIT_WD_TRIG_EARLY … #define TPS6594_BIT_WD_ANSW_EARLY … #define TPS6594_BIT_WD_SEQ_ERR … #define TPS6594_BIT_WD_ANSW_ERR … #define TPS6594_BIT_WD_FAIL_INT … #define TPS6594_BIT_WD_RST_INT … /* WD_THR_CFG register field definition */ #define TPS6594_MASK_WD_RST_TH … #define TPS6594_MASK_WD_FAIL_TH … #define TPS6594_BIT_WD_EN … #define TPS6594_BIT_WD_RST_EN … /* WD_FAIL_CNT_REG register field definition */ #define TPS6594_MASK_WD_FAIL_CNT … #define TPS6594_BIT_WD_FIRST_OK … #define TPS6594_BIT_WD_BAD_EVENT … /* CRC8 polynomial for I2C & SPI protocols */ #define TPS6594_CRC8_POLYNOMIAL … /* IRQs */ enum tps6594_irqs { … }; #define TPS6594_IRQ_NAME_BUCK1_OV … #define TPS6594_IRQ_NAME_BUCK1_UV … #define TPS6594_IRQ_NAME_BUCK1_SC … #define TPS6594_IRQ_NAME_BUCK1_ILIM … #define TPS6594_IRQ_NAME_BUCK2_OV … #define TPS6594_IRQ_NAME_BUCK2_UV … #define TPS6594_IRQ_NAME_BUCK2_SC … #define TPS6594_IRQ_NAME_BUCK2_ILIM … #define TPS6594_IRQ_NAME_BUCK3_OV … #define TPS6594_IRQ_NAME_BUCK3_UV … #define TPS6594_IRQ_NAME_BUCK3_SC … #define TPS6594_IRQ_NAME_BUCK3_ILIM … #define TPS6594_IRQ_NAME_BUCK4_OV … #define TPS6594_IRQ_NAME_BUCK4_UV … #define TPS6594_IRQ_NAME_BUCK4_SC … #define TPS6594_IRQ_NAME_BUCK4_ILIM … #define TPS6594_IRQ_NAME_BUCK5_OV … #define TPS6594_IRQ_NAME_BUCK5_UV … #define TPS6594_IRQ_NAME_BUCK5_SC … #define TPS6594_IRQ_NAME_BUCK5_ILIM … #define TPS6594_IRQ_NAME_LDO1_OV … #define TPS6594_IRQ_NAME_LDO1_UV … #define TPS6594_IRQ_NAME_LDO1_SC … #define TPS6594_IRQ_NAME_LDO1_ILIM … #define TPS6594_IRQ_NAME_LDO2_OV … #define TPS6594_IRQ_NAME_LDO2_UV … #define TPS6594_IRQ_NAME_LDO2_SC … #define TPS6594_IRQ_NAME_LDO2_ILIM … #define TPS6594_IRQ_NAME_LDO3_OV … #define TPS6594_IRQ_NAME_LDO3_UV … #define TPS6594_IRQ_NAME_LDO3_SC … #define TPS6594_IRQ_NAME_LDO3_ILIM … #define TPS6594_IRQ_NAME_LDO4_OV … #define TPS6594_IRQ_NAME_LDO4_UV … #define TPS6594_IRQ_NAME_LDO4_SC … #define TPS6594_IRQ_NAME_LDO4_ILIM … #define TPS6594_IRQ_NAME_VCCA_OV … #define TPS6594_IRQ_NAME_VCCA_UV … #define TPS6594_IRQ_NAME_VMON1_OV … #define TPS6594_IRQ_NAME_VMON1_UV … #define TPS6594_IRQ_NAME_VMON1_RV … #define TPS6594_IRQ_NAME_VMON2_OV … #define TPS6594_IRQ_NAME_VMON2_UV … #define TPS6594_IRQ_NAME_VMON2_RV … #define TPS6594_IRQ_NAME_GPIO9 … #define TPS6594_IRQ_NAME_GPIO10 … #define TPS6594_IRQ_NAME_GPIO11 … #define TPS6594_IRQ_NAME_GPIO1 … #define TPS6594_IRQ_NAME_GPIO2 … #define TPS6594_IRQ_NAME_GPIO3 … #define TPS6594_IRQ_NAME_GPIO4 … #define TPS6594_IRQ_NAME_GPIO5 … #define TPS6594_IRQ_NAME_GPIO6 … #define TPS6594_IRQ_NAME_GPIO7 … #define TPS6594_IRQ_NAME_GPIO8 … #define TPS6594_IRQ_NAME_NPWRON_START … #define TPS6594_IRQ_NAME_ENABLE … #define TPS6594_IRQ_NAME_FSD … #define TPS6594_IRQ_NAME_SOFT_REBOOT … #define TPS6594_IRQ_NAME_BIST_PASS … #define TPS6594_IRQ_NAME_EXT_CLK … #define TPS6594_IRQ_NAME_TWARN … #define TPS6594_IRQ_NAME_TSD_ORD … #define TPS6594_IRQ_NAME_BIST_FAIL … #define TPS6594_IRQ_NAME_REG_CRC_ERR … #define TPS6594_IRQ_NAME_RECOV_CNT … #define TPS6594_IRQ_NAME_SPMI_ERR … #define TPS6594_IRQ_NAME_NPWRON_LONG … #define TPS6594_IRQ_NAME_NINT_READBACK … #define TPS6594_IRQ_NAME_NRSTOUT_READBACK … #define TPS6594_IRQ_NAME_TSD_IMM … #define TPS6594_IRQ_NAME_VCCA_OVP … #define TPS6594_IRQ_NAME_PFSM_ERR … #define TPS6594_IRQ_NAME_IMM_SHUTDOWN … #define TPS6594_IRQ_NAME_ORD_SHUTDOWN … #define TPS6594_IRQ_NAME_MCU_PWR_ERR … #define TPS6594_IRQ_NAME_SOC_PWR_ERR … #define TPS6594_IRQ_NAME_COMM_FRM_ERR … #define TPS6594_IRQ_NAME_COMM_CRC_ERR … #define TPS6594_IRQ_NAME_COMM_ADR_ERR … #define TPS6594_IRQ_NAME_EN_DRV_READBACK … #define TPS6594_IRQ_NAME_NRSTOUT_SOC_READBACK … #define TPS6594_IRQ_NAME_ESM_SOC_PIN … #define TPS6594_IRQ_NAME_ESM_SOC_FAIL … #define TPS6594_IRQ_NAME_ESM_SOC_RST … #define TPS6594_IRQ_NAME_TIMER … #define TPS6594_IRQ_NAME_ALARM … #define TPS6594_IRQ_NAME_POWERUP … /* IRQs */ enum tps65224_irqs { … }; #define TPS65224_IRQ_NAME_BUCK1_UVOV … #define TPS65224_IRQ_NAME_BUCK2_UVOV … #define TPS65224_IRQ_NAME_BUCK3_UVOV … #define TPS65224_IRQ_NAME_BUCK4_UVOV … #define TPS65224_IRQ_NAME_LDO1_UVOV … #define TPS65224_IRQ_NAME_LDO2_UVOV … #define TPS65224_IRQ_NAME_LDO3_UVOV … #define TPS65224_IRQ_NAME_VCCA_UVOV … #define TPS65224_IRQ_NAME_VMON1_UVOV … #define TPS65224_IRQ_NAME_VMON2_UVOV … #define TPS65224_IRQ_NAME_GPIO1 … #define TPS65224_IRQ_NAME_GPIO2 … #define TPS65224_IRQ_NAME_GPIO3 … #define TPS65224_IRQ_NAME_GPIO4 … #define TPS65224_IRQ_NAME_GPIO5 … #define TPS65224_IRQ_NAME_GPIO6 … #define TPS65224_IRQ_NAME_VSENSE … #define TPS65224_IRQ_NAME_ENABLE … #define TPS65224_IRQ_NAME_PB_SHORT … #define TPS65224_IRQ_NAME_FSD … #define TPS65224_IRQ_NAME_SOFT_REBOOT … #define TPS65224_IRQ_NAME_BIST_PASS … #define TPS65224_IRQ_NAME_EXT_CLK … #define TPS65224_IRQ_NAME_REG_UNLOCK … #define TPS65224_IRQ_NAME_TWARN … #define TPS65224_IRQ_NAME_PB_LONG … #define TPS65224_IRQ_NAME_PB_FALL … #define TPS65224_IRQ_NAME_PB_RISE … #define TPS65224_IRQ_NAME_ADC_CONV_READY … #define TPS65224_IRQ_NAME_TSD_ORD … #define TPS65224_IRQ_NAME_BIST_FAIL … #define TPS65224_IRQ_NAME_REG_CRC_ERR … #define TPS65224_IRQ_NAME_RECOV_CNT … #define TPS65224_IRQ_NAME_TSD_IMM … #define TPS65224_IRQ_NAME_VCCA_OVP … #define TPS65224_IRQ_NAME_PFSM_ERR … #define TPS65224_IRQ_NAME_BG_XMON … #define TPS65224_IRQ_NAME_IMM_SHUTDOWN … #define TPS65224_IRQ_NAME_ORD_SHUTDOWN … #define TPS65224_IRQ_NAME_MCU_PWR_ERR … #define TPS65224_IRQ_NAME_SOC_PWR_ERR … #define TPS65224_IRQ_NAME_COMM_ERR … #define TPS65224_IRQ_NAME_I2C2_ERR … #define TPS65224_IRQ_NAME_POWERUP … /** * struct tps6594 - device private data structure * * @dev: MFD parent device * @chip_id: chip ID * @reg: I2C slave address or SPI chip select number * @use_crc: if true, use CRC for I2C and SPI interface protocols * @regmap: regmap for accessing the device registers * @irq: irq generated by the device * @irq_data: regmap irq data used for the irq chip */ struct tps6594 { … }; extern const struct regmap_access_table tps6594_volatile_table; extern const struct regmap_access_table tps65224_volatile_table; int tps6594_device_init(struct tps6594 *tps, bool enable_crc); #endif /* __LINUX_MFD_TPS6594_H */
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