/* * Copyright 2007 Stephane Marchesin * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragr) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "priv.h" #include "regs.h" #include <core/client.h> #include <core/gpuobj.h> #include <engine/fifo.h> #include <engine/fifo/chan.h> #include <subdev/instmem.h> #include <subdev/timer.h> static u32 nv04_gr_ctx_regs[] = …; #define nv04_gr(p) … struct nv04_gr { … }; #define nv04_gr_chan(p) … struct nv04_gr_chan { … }; /******************************************************************************* * Graphics object classes ******************************************************************************/ /* * Software methods, why they are needed, and how they all work: * * NV04 and NV05 keep most of the state in PGRAPH context itself, but some * 2d engine settings are kept inside the grobjs themselves. The grobjs are * 3 words long on both. grobj format on NV04 is: * * word 0: * - bits 0-7: class * - bit 12: color key active * - bit 13: clip rect active * - bit 14: if set, destination surface is swizzled and taken from buffer 5 * [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken * from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or * NV03_CONTEXT_SURFACE_DST]. * - bits 15-17: 2d operation [aka patch config] * - bit 24: patch valid [enables rendering using this object] * - bit 25: surf3d valid [for tex_tri and multitex_tri only] * word 1: * - bits 0-1: mono format * - bits 8-13: color format * - bits 16-31: DMA_NOTIFY instance * word 2: * - bits 0-15: DMA_A instance * - bits 16-31: DMA_B instance * * On NV05 it's: * * word 0: * - bits 0-7: class * - bit 12: color key active * - bit 13: clip rect active * - bit 14: if set, destination surface is swizzled and taken from buffer 5 * [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken * from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or * NV03_CONTEXT_SURFACE_DST]. * - bits 15-17: 2d operation [aka patch config] * - bits 20-22: dither mode * - bit 24: patch valid [enables rendering using this object] * - bit 25: surface_dst/surface_color/surf2d/surf3d valid * - bit 26: surface_src/surface_zeta valid * - bit 27: pattern valid * - bit 28: rop valid * - bit 29: beta1 valid * - bit 30: beta4 valid * word 1: * - bits 0-1: mono format * - bits 8-13: color format * - bits 16-31: DMA_NOTIFY instance * word 2: * - bits 0-15: DMA_A instance * - bits 16-31: DMA_B instance * * NV05 will set/unset the relevant valid bits when you poke the relevant * object-binding methods with object of the proper type, or with the NULL * type. It'll only allow rendering using the grobj if all needed objects * are bound. The needed set of objects depends on selected operation: for * example rop object is needed by ROP_AND, but not by SRCCOPY_AND. * * NV04 doesn't have these methods implemented at all, and doesn't have the * relevant bits in grobj. Instead, it'll allow rendering whenever bit 24 * is set. So we have to emulate them in software, internally keeping the * same bits as NV05 does. Since grobjs are aligned to 16 bytes on nv04, * but the last word isn't actually used for anything, we abuse it for this * purpose. * * Actually, NV05 can optionally check bit 24 too, but we disable this since * there's no use for it. * * For unknown reasons, NV04 implements surf3d binding in hardware as an * exception. Also for unknown reasons, NV04 doesn't implement the clipping * methods on the surf3d object, so we have to emulate them too. */ static void nv04_gr_set_ctx1(struct nvkm_device *device, u32 inst, u32 mask, u32 value) { … } static void nv04_gr_set_ctx_val(struct nvkm_device *device, u32 inst, u32 mask, u32 value) { … } static bool nv04_gr_mthd_set_operation(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv04_gr_mthd_surf3d_clip_h(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv04_gr_mthd_surf3d_clip_v(struct nvkm_device *device, u32 inst, u32 data) { … } static u8 nv04_gr_mthd_bind_class(struct nvkm_device *device, u32 inst) { … } static bool nv04_gr_mthd_bind_surf2d(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv04_gr_mthd_bind_surf2d_swzsurf(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv01_gr_mthd_bind_patt(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv04_gr_mthd_bind_patt(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv04_gr_mthd_bind_rop(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv04_gr_mthd_bind_beta1(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv04_gr_mthd_bind_beta4(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv04_gr_mthd_bind_surf_dst(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv04_gr_mthd_bind_surf_src(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv04_gr_mthd_bind_surf_color(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv04_gr_mthd_bind_surf_zeta(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv01_gr_mthd_bind_clip(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv01_gr_mthd_bind_chroma(struct nvkm_device *device, u32 inst, u32 data) { … } static bool nv03_gr_mthd_gdi(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv04_gr_mthd_gdi(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv01_gr_mthd_blit(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv04_gr_mthd_blit(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv04_gr_mthd_iifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv01_gr_mthd_ifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv04_gr_mthd_ifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv03_gr_mthd_sifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv04_gr_mthd_sifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv03_gr_mthd_sifm(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv04_gr_mthd_sifm(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv04_gr_mthd_surf3d(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv03_gr_mthd_ttri(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv01_gr_mthd_prim(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv04_gr_mthd_prim(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static bool nv04_gr_mthd(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) { … } static int nv04_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) { … } const struct nvkm_object_func nv04_gr_object = …; /******************************************************************************* * PGRAPH context ******************************************************************************/ static struct nv04_gr_chan * nv04_gr_channel(struct nv04_gr *gr) { … } static int nv04_gr_load_context(struct nv04_gr_chan *chan, int chid) { … } static int nv04_gr_unload_context(struct nv04_gr_chan *chan) { … } static void nv04_gr_context_switch(struct nv04_gr *gr) { … } static u32 *ctx_reg(struct nv04_gr_chan *chan, u32 reg) { … } static void * nv04_gr_chan_dtor(struct nvkm_object *object) { … } static int nv04_gr_chan_fini(struct nvkm_object *object, bool suspend) { … } static const struct nvkm_object_func nv04_gr_chan = …; static int nv04_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch, const struct nvkm_oclass *oclass, struct nvkm_object **pobject) { … } /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ bool nv04_gr_idle(struct nvkm_gr *gr) { … } static const struct nvkm_bitfield nv04_gr_intr_name[] = …; static const struct nvkm_bitfield nv04_gr_nstatus[] = …; const struct nvkm_bitfield nv04_gr_nsource[] = …; static void nv04_gr_intr(struct nvkm_gr *base) { … } static int nv04_gr_init(struct nvkm_gr *base) { … } static const struct nvkm_gr_func nv04_gr = …; int nv04_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) { … }
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