/* SPDX-License-Identifier: MIT */ #define NV04_PFB_BOOT_0 … #define NV04_PFB_BOOT_0_RAM_AMOUNT … #define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB … #define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB … #define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB … #define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB … #define NV04_PFB_BOOT_0_RAM_WIDTH_128 … #define NV04_PFB_BOOT_0_RAM_TYPE … #define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT … #define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT … #define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK … #define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT … #define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT … #define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 … #define NV04_PFB_BOOT_0_UMA_ENABLE … #define NV04_PFB_BOOT_0_UMA_SIZE … #define NV04_PFB_DEBUG_0 … #define NV04_PFB_DEBUG_0_PAGE_MODE … #define NV04_PFB_DEBUG_0_REFRESH_OFF … #define NV04_PFB_DEBUG_0_REFRESH_COUNTX64 … #define NV04_PFB_DEBUG_0_REFRESH_SLOW_CLK … #define NV04_PFB_DEBUG_0_SAFE_MODE … #define NV04_PFB_DEBUG_0_ALOM_ENABLE … #define NV04_PFB_DEBUG_0_CASOE … #define NV04_PFB_DEBUG_0_CKE_INVERT … #define NV04_PFB_DEBUG_0_REFINC … #define NV04_PFB_DEBUG_0_SAVE_POWER_OFF … #define NV04_PFB_CFG0 … #define NV04_PFB_CFG0_SCRAMBLE … #define NV04_PFB_CFG1 … #define NV04_PFB_FIFO_DATA … #define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK … #define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT … #define NV10_PFB_REFCTRL … #define NV10_PFB_REFCTRL_VALID_1 … #define NV04_PFB_PAD … #define NV04_PFB_PAD_CKE_NORMAL … #define NV10_PFB_TILE(i) … #define NV10_PFB_TILE__SIZE … #define NV10_PFB_TLIMIT(i) … #define NV10_PFB_TSIZE(i) … #define NV10_PFB_TSTATUS(i) … #define NV04_PFB_REF … #define NV04_PFB_REF_CMD_REFRESH … #define NV04_PFB_PRE … #define NV04_PFB_PRE_CMD_PRECHARGE … #define NV20_PFB_ZCOMP(i) … #define NV20_PFB_ZCOMP_MODE_32 … #define NV20_PFB_ZCOMP_EN … #define NV25_PFB_ZCOMP_MODE_16 … #define NV25_PFB_ZCOMP_MODE_32 … #define NV10_PFB_CLOSE_PAGE2 … #define NV04_PFB_SCRAMBLE(i) … #define NV40_PFB_TILE(i) … #define NV40_PFB_TILE__SIZE_0 … #define NV40_PFB_TILE__SIZE_1 … #define NV40_PFB_TLIMIT(i) … #define NV40_PFB_TSIZE(i) … #define NV40_PFB_TSTATUS(i) … #define NV40_PFB_UNK_800 … #define NV_PEXTDEV_BOOT_0 … #define NV_PEXTDEV_BOOT_0_RAMCFG … #define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT … #define NV_PEXTDEV_BOOT_3 … #define NV_RAMIN … #define NV_RAMHT_HANDLE_OFFSET … #define NV_RAMHT_CONTEXT_OFFSET … #define NV_RAMHT_CONTEXT_VALID … #define NV_RAMHT_CONTEXT_CHANNEL_SHIFT … #define NV_RAMHT_CONTEXT_ENGINE_SHIFT … #define NV_RAMHT_CONTEXT_ENGINE_SW … #define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS … #define NV_RAMHT_CONTEXT_INSTANCE_SHIFT … #define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT … #define NV40_RAMHT_CONTEXT_ENGINE_SHIFT … #define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT … /* Some object classes we care about in the drm */ #define NV_CLASS_DMA_FROM_MEMORY … #define NV_CLASS_DMA_TO_MEMORY … #define NV_CLASS_NULL … #define NV_CLASS_DMA_IN_MEMORY … #define NV03_USER(i) … #define NV03_USER__SIZE … #define NV10_USER__SIZE … #define NV03_USER_SIZE … #define NV03_USER_DMA_PUT(i) … #define NV03_USER_DMA_PUT__SIZE … #define NV10_USER_DMA_PUT__SIZE … #define NV03_USER_DMA_GET(i) … #define NV03_USER_DMA_GET__SIZE … #define NV10_USER_DMA_GET__SIZE … #define NV03_USER_REF_CNT(i) … #define NV03_USER_REF_CNT__SIZE … #define NV10_USER_REF_CNT__SIZE … #define NV40_USER(i) … #define NV40_USER_SIZE … #define NV40_USER_DMA_PUT(i) … #define NV40_USER_DMA_PUT__SIZE … #define NV40_USER_DMA_GET(i) … #define NV40_USER_DMA_GET__SIZE … #define NV40_USER_REF_CNT(i) … #define NV40_USER_REF_CNT__SIZE … #define NV50_USER(i) … #define NV50_USER_SIZE … #define NV50_USER_DMA_PUT(i) … #define NV50_USER_DMA_PUT__SIZE … #define NV50_USER_DMA_GET(i) … #define NV50_USER_DMA_GET__SIZE … #define NV50_USER_REF_CNT(i) … #define NV50_USER_REF_CNT__SIZE … #define NV03_FIFO_SIZE … #define NV03_PMC_BOOT_0 … #define NV03_PMC_BOOT_1 … #define NV03_PMC_INTR_0 … #define NV_PMC_INTR_0_PFIFO_PENDING … #define NV_PMC_INTR_0_PGRAPH_PENDING … #define NV_PMC_INTR_0_NV50_I2C_PENDING … #define NV_PMC_INTR_0_CRTC0_PENDING … #define NV_PMC_INTR_0_CRTC1_PENDING … #define NV_PMC_INTR_0_NV50_DISPLAY_PENDING … #define NV_PMC_INTR_0_CRTCn_PENDING … #define NV03_PMC_INTR_EN_0 … #define NV_PMC_INTR_EN_0_MASTER_ENABLE … #define NV03_PMC_ENABLE … #define NV_PMC_ENABLE_PFIFO … #define NV_PMC_ENABLE_PGRAPH … /* Disabling the below bit breaks newer (G7X only?) mobile chipsets, * the card will hang early on in the X init process. */ #define NV_PMC_ENABLE_UNK13 … #define NV40_PMC_GRAPH_UNITS … #define NV40_PMC_BACKLIGHT … #define NV40_PMC_BACKLIGHT_MASK … #define NV40_PMC_1700 … #define NV40_PMC_1704 … #define NV40_PMC_1708 … #define NV40_PMC_170C … /* probably PMC ? */ #define NV50_PUNK_BAR0_PRAMIN … #define NV50_PUNK_BAR_CFG_BASE … #define NV50_PUNK_BAR_CFG_BASE_VALID … #define NV50_PUNK_BAR1_CTXDMA … #define NV50_PUNK_BAR1_CTXDMA_VALID … #define NV50_PUNK_BAR3_CTXDMA … #define NV50_PUNK_BAR3_CTXDMA_VALID … #define NV50_PUNK_UNK1710 … #define NV04_PBUS_PCI_NV_1 … #define NV04_PBUS_PCI_NV_19 … #define NV04_PBUS_PCI_NV_20 … #define NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED … #define NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED … #define NV04_PTIMER_INTR_0 … #define NV04_PTIMER_INTR_EN_0 … #define NV04_PTIMER_NUMERATOR … #define NV04_PTIMER_DENOMINATOR … #define NV04_PTIMER_TIME_0 … #define NV04_PTIMER_TIME_1 … #define NV04_PTIMER_ALARM_0 … #define NV04_PGRAPH_DEBUG_0 … #define NV04_PGRAPH_DEBUG_1 … #define NV04_PGRAPH_DEBUG_2 … #define NV04_PGRAPH_DEBUG_3 … #define NV10_PGRAPH_DEBUG_4 … #define NV03_PGRAPH_INTR … #define NV03_PGRAPH_NSTATUS … #define NV04_PGRAPH_NSTATUS_STATE_IN_USE … #define NV04_PGRAPH_NSTATUS_INVALID_STATE … #define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT … #define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT … #define NV10_PGRAPH_NSTATUS_STATE_IN_USE … #define NV10_PGRAPH_NSTATUS_INVALID_STATE … #define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT … #define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT … #define NV03_PGRAPH_NSOURCE … #define NV03_PGRAPH_NSOURCE_NOTIFICATION … #define NV03_PGRAPH_NSOURCE_DATA_ERROR … #define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR … #define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION … #define NV03_PGRAPH_NSOURCE_LIMIT_COLOR … #define NV03_PGRAPH_NSOURCE_LIMIT_ZETA … #define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD … #define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION … #define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION … #define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION … #define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION … #define NV03_PGRAPH_NSOURCE_STATE_INVALID … #define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY … #define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE … #define NV03_PGRAPH_NSOURCE_METHOD_CNT … #define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION … #define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION … #define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A … #define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B … #define NV03_PGRAPH_INTR_EN … #define NV40_PGRAPH_INTR_EN … #define NV_PGRAPH_INTR_NOTIFY … #define NV_PGRAPH_INTR_MISSING_HW … #define NV_PGRAPH_INTR_CONTEXT_SWITCH … #define NV_PGRAPH_INTR_BUFFER_NOTIFY … #define NV_PGRAPH_INTR_ERROR … #define NV10_PGRAPH_CTX_CONTROL … #define NV10_PGRAPH_CTX_USER … #define NV10_PGRAPH_CTX_SWITCH(i) … #define NV04_PGRAPH_CTX_SWITCH1 … #define NV10_PGRAPH_CTX_CACHE(i, j) … #define NV04_PGRAPH_CTX_SWITCH2 … #define NV04_PGRAPH_CTX_SWITCH3 … #define NV04_PGRAPH_CTX_SWITCH4 … #define NV04_PGRAPH_CTX_CONTROL … #define NV04_PGRAPH_CTX_USER … #define NV04_PGRAPH_CTX_CACHE1 … #define NV03_PGRAPH_CTX_CONTROL … #define NV03_PGRAPH_CTX_USER … #define NV04_PGRAPH_CTX_CACHE2 … #define NV04_PGRAPH_CTX_CACHE3 … #define NV04_PGRAPH_CTX_CACHE4 … #define NV40_PGRAPH_CTXCTL_0304 … #define NV40_PGRAPH_CTXCTL_0304_XFER_CTX … #define NV40_PGRAPH_CTXCTL_UCODE_STAT … #define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK … #define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT … #define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK … #define NV40_PGRAPH_CTXCTL_0310 … #define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE … #define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD … #define NV40_PGRAPH_CTXCTL_030C … #define NV40_PGRAPH_CTXCTL_UCODE_INDEX … #define NV40_PGRAPH_CTXCTL_UCODE_DATA … #define NV40_PGRAPH_CTXCTL_CUR … #define NV40_PGRAPH_CTXCTL_CUR_LOADED … #define NV40_PGRAPH_CTXCTL_CUR_INSTANCE … #define NV40_PGRAPH_CTXCTL_NEXT … #define NV40_PGRAPH_CTXCTL_NEXT_INSTANCE … #define NV50_PGRAPH_CTXCTL_CUR … #define NV50_PGRAPH_CTXCTL_CUR_LOADED … #define NV50_PGRAPH_CTXCTL_CUR_INSTANCE … #define NV50_PGRAPH_CTXCTL_NEXT … #define NV50_PGRAPH_CTXCTL_NEXT_INSTANCE … #define NV03_PGRAPH_ABS_X_RAM … #define NV03_PGRAPH_ABS_Y_RAM … #define NV03_PGRAPH_X_MISC … #define NV03_PGRAPH_Y_MISC … #define NV04_PGRAPH_VALID1 … #define NV04_PGRAPH_SOURCE_COLOR … #define NV04_PGRAPH_MISC24_0 … #define NV03_PGRAPH_XY_LOGIC_MISC0 … #define NV03_PGRAPH_XY_LOGIC_MISC1 … #define NV03_PGRAPH_XY_LOGIC_MISC2 … #define NV03_PGRAPH_XY_LOGIC_MISC3 … #define NV03_PGRAPH_CLIPX_0 … #define NV03_PGRAPH_CLIPX_1 … #define NV03_PGRAPH_CLIPY_0 … #define NV03_PGRAPH_CLIPY_1 … #define NV03_PGRAPH_ABS_ICLIP_XMAX … #define NV03_PGRAPH_ABS_ICLIP_YMAX … #define NV03_PGRAPH_ABS_UCLIP_XMIN … #define NV03_PGRAPH_ABS_UCLIP_YMIN … #define NV03_PGRAPH_ABS_UCLIP_XMAX … #define NV03_PGRAPH_ABS_UCLIP_YMAX … #define NV03_PGRAPH_ABS_UCLIPA_XMIN … #define NV03_PGRAPH_ABS_UCLIPA_YMIN … #define NV03_PGRAPH_ABS_UCLIPA_XMAX … #define NV03_PGRAPH_ABS_UCLIPA_YMAX … #define NV04_PGRAPH_MISC24_1 … #define NV04_PGRAPH_MISC24_2 … #define NV04_PGRAPH_VALID2 … #define NV04_PGRAPH_PASSTHRU_0 … #define NV04_PGRAPH_PASSTHRU_1 … #define NV04_PGRAPH_PASSTHRU_2 … #define NV10_PGRAPH_DIMX_TEXTURE … #define NV10_PGRAPH_WDIMX_TEXTURE … #define NV04_PGRAPH_COMBINE_0_ALPHA … #define NV04_PGRAPH_COMBINE_0_COLOR … #define NV04_PGRAPH_COMBINE_1_ALPHA … #define NV04_PGRAPH_COMBINE_1_COLOR … #define NV04_PGRAPH_FORMAT_0 … #define NV04_PGRAPH_FORMAT_1 … #define NV04_PGRAPH_FILTER_0 … #define NV04_PGRAPH_FILTER_1 … #define NV03_PGRAPH_MONO_COLOR0 … #define NV04_PGRAPH_ROP3 … #define NV04_PGRAPH_BETA_AND … #define NV04_PGRAPH_BETA_PREMULT … #define NV04_PGRAPH_LIMIT_VIOL_PIX … #define NV04_PGRAPH_FORMATS … #define NV10_PGRAPH_DEBUG_2 … #define NV04_PGRAPH_BOFFSET0 … #define NV04_PGRAPH_BOFFSET1 … #define NV04_PGRAPH_BOFFSET2 … #define NV04_PGRAPH_BOFFSET3 … #define NV04_PGRAPH_BOFFSET4 … #define NV04_PGRAPH_BOFFSET5 … #define NV04_PGRAPH_BBASE0 … #define NV04_PGRAPH_BBASE1 … #define NV04_PGRAPH_BBASE2 … #define NV04_PGRAPH_BBASE3 … #define NV04_PGRAPH_BBASE4 … #define NV04_PGRAPH_BBASE5 … #define NV04_PGRAPH_BPITCH0 … #define NV04_PGRAPH_BPITCH1 … #define NV04_PGRAPH_BPITCH2 … #define NV04_PGRAPH_BPITCH3 … #define NV04_PGRAPH_BPITCH4 … #define NV04_PGRAPH_BLIMIT0 … #define NV04_PGRAPH_BLIMIT1 … #define NV04_PGRAPH_BLIMIT2 … #define NV04_PGRAPH_BLIMIT3 … #define NV04_PGRAPH_BLIMIT4 … #define NV04_PGRAPH_BLIMIT5 … #define NV04_PGRAPH_BSWIZZLE2 … #define NV04_PGRAPH_BSWIZZLE5 … #define NV03_PGRAPH_STATUS … #define NV04_PGRAPH_STATUS … #define NV40_PGRAPH_STATUS_SYNC_STALL … #define NV04_PGRAPH_TRAPPED_ADDR … #define NV04_PGRAPH_TRAPPED_DATA … #define NV04_PGRAPH_SURFACE … #define NV10_PGRAPH_TRAPPED_DATA_HIGH … #define NV04_PGRAPH_STATE … #define NV10_PGRAPH_SURFACE … #define NV04_PGRAPH_NOTIFY … #define NV10_PGRAPH_STATE … #define NV10_PGRAPH_NOTIFY … #define NV04_PGRAPH_FIFO … #define NV04_PGRAPH_BPIXEL … #define NV10_PGRAPH_RDI_INDEX … #define NV04_PGRAPH_FFINTFC_ST2 … #define NV10_PGRAPH_RDI_DATA … #define NV04_PGRAPH_DMA_PITCH … #define NV10_PGRAPH_FFINTFC_FIFO_PTR … #define NV04_PGRAPH_DVD_COLORFMT … #define NV10_PGRAPH_FFINTFC_ST2 … #define NV04_PGRAPH_SCALED_FORMAT … #define NV10_PGRAPH_FFINTFC_ST2_DL … #define NV10_PGRAPH_FFINTFC_ST2_DH … #define NV10_PGRAPH_DMA_PITCH … #define NV10_PGRAPH_DVD_COLORFMT … #define NV10_PGRAPH_SCALED_FORMAT … #define NV20_PGRAPH_CHANNEL_CTX_TABLE … #define NV20_PGRAPH_CHANNEL_CTX_POINTER … #define NV20_PGRAPH_CHANNEL_CTX_XFER … #define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD … #define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE … #define NV04_PGRAPH_PATT_COLOR0 … #define NV04_PGRAPH_PATT_COLOR1 … #define NV04_PGRAPH_PATTERN … #define NV04_PGRAPH_PATTERN_SHAPE … #define NV04_PGRAPH_CHROMA … #define NV04_PGRAPH_CONTROL0 … #define NV04_PGRAPH_CONTROL1 … #define NV04_PGRAPH_CONTROL2 … #define NV04_PGRAPH_BLEND … #define NV04_PGRAPH_STORED_FMT … #define NV04_PGRAPH_PATT_COLORRAM … #define NV20_PGRAPH_TILE(i) … #define NV20_PGRAPH_TLIMIT(i) … #define NV20_PGRAPH_TSIZE(i) … #define NV20_PGRAPH_TSTATUS(i) … #define NV20_PGRAPH_ZCOMP(i) … #define NV10_PGRAPH_TILE(i) … #define NV10_PGRAPH_TLIMIT(i) … #define NV10_PGRAPH_TSIZE(i) … #define NV10_PGRAPH_TSTATUS(i) … #define NV04_PGRAPH_U_RAM … #define NV47_PGRAPH_TILE(i) … #define NV47_PGRAPH_TLIMIT(i) … #define NV47_PGRAPH_TSIZE(i) … #define NV47_PGRAPH_TSTATUS(i) … #define NV04_PGRAPH_V_RAM … #define NV04_PGRAPH_W_RAM … #define NV10_PGRAPH_COMBINER0_IN_ALPHA … #define NV10_PGRAPH_COMBINER1_IN_ALPHA … #define NV10_PGRAPH_COMBINER0_IN_RGB … #define NV10_PGRAPH_COMBINER1_IN_RGB … #define NV10_PGRAPH_COMBINER_COLOR0 … #define NV10_PGRAPH_COMBINER_COLOR1 … #define NV10_PGRAPH_COMBINER0_OUT_ALPHA … #define NV10_PGRAPH_COMBINER1_OUT_ALPHA … #define NV10_PGRAPH_COMBINER0_OUT_RGB … #define NV10_PGRAPH_COMBINER1_OUT_RGB … #define NV10_PGRAPH_COMBINER_FINAL0 … #define NV10_PGRAPH_COMBINER_FINAL1 … #define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL … #define NV10_PGRAPH_WINDOWCLIP_VERTICAL … #define NV10_PGRAPH_XFMODE0 … #define NV10_PGRAPH_XFMODE1 … #define NV10_PGRAPH_GLOBALSTATE0 … #define NV10_PGRAPH_GLOBALSTATE1 … #define NV10_PGRAPH_PIPE_ADDRESS … #define NV10_PGRAPH_PIPE_DATA … #define NV04_PGRAPH_DMA_START_0 … #define NV04_PGRAPH_DMA_START_1 … #define NV04_PGRAPH_DMA_LENGTH … #define NV04_PGRAPH_DMA_MISC … #define NV04_PGRAPH_DMA_DATA_0 … #define NV04_PGRAPH_DMA_DATA_1 … #define NV04_PGRAPH_DMA_RM … #define NV04_PGRAPH_DMA_A_XLATE_INST … #define NV04_PGRAPH_DMA_A_CONTROL … #define NV04_PGRAPH_DMA_A_LIMIT … #define NV04_PGRAPH_DMA_A_TLB_PTE … #define NV04_PGRAPH_DMA_A_TLB_TAG … #define NV04_PGRAPH_DMA_A_ADJ_OFFSET … #define NV04_PGRAPH_DMA_A_OFFSET … #define NV04_PGRAPH_DMA_A_SIZE … #define NV04_PGRAPH_DMA_A_Y_SIZE … #define NV04_PGRAPH_DMA_B_XLATE_INST … #define NV04_PGRAPH_DMA_B_CONTROL … #define NV04_PGRAPH_DMA_B_LIMIT … #define NV04_PGRAPH_DMA_B_TLB_PTE … #define NV04_PGRAPH_DMA_B_TLB_TAG … #define NV04_PGRAPH_DMA_B_ADJ_OFFSET … #define NV04_PGRAPH_DMA_B_OFFSET … #define NV04_PGRAPH_DMA_B_SIZE … #define NV04_PGRAPH_DMA_B_Y_SIZE … #define NV40_PGRAPH_TILE1(i) … #define NV40_PGRAPH_TLIMIT1(i) … #define NV40_PGRAPH_TSIZE1(i) … #define NV40_PGRAPH_TSTATUS1(i) … /* It's a guess that this works on NV03. Confirmed on NV04, though */ #define NV04_PFIFO_DELAY_0 … #define NV04_PFIFO_DMA_TIMESLICE … #define NV04_PFIFO_NEXT_CHANNEL … #define NV03_PFIFO_INTR_0 … #define NV03_PFIFO_INTR_EN_0 … #define NV_PFIFO_INTR_CACHE_ERROR … #define NV_PFIFO_INTR_RUNOUT … #define NV_PFIFO_INTR_RUNOUT_OVERFLOW … #define NV_PFIFO_INTR_DMA_PUSHER … #define NV_PFIFO_INTR_DMA_PT … #define NV_PFIFO_INTR_SEMAPHORE … #define NV_PFIFO_INTR_ACQUIRE_TIMEOUT … #define NV03_PFIFO_RAMHT … #define NV03_PFIFO_RAMFC … #define NV03_PFIFO_RAMRO … #define NV40_PFIFO_RAMFC … #define NV03_PFIFO_CACHES … #define NV04_PFIFO_MODE … #define NV04_PFIFO_DMA … #define NV04_PFIFO_SIZE … #define NV50_PFIFO_CTX_TABLE(c) … #define NV50_PFIFO_CTX_TABLE__SIZE … #define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED … #define NV50_PFIFO_CTX_TABLE_UNK30_BAD … #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 … #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 … #define NV03_PFIFO_CACHE0_PUSH0 … #define NV03_PFIFO_CACHE0_PULL0 … #define NV04_PFIFO_CACHE0_PULL0 … #define NV04_PFIFO_CACHE0_PULL1 … #define NV03_PFIFO_CACHE1_PUSH0 … #define NV03_PFIFO_CACHE1_PUSH1 … #define NV03_PFIFO_CACHE1_PUSH1_DMA … #define NV40_PFIFO_CACHE1_PUSH1_DMA … #define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK … #define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK … #define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK … #define NV03_PFIFO_CACHE1_PUT … #define NV04_PFIFO_CACHE1_DMA_PUSH … #define NV04_PFIFO_CACHE1_DMA_FETCH … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 … #define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 … #define NV_PFIFO_CACHE1_ENDIAN … #define NV_PFIFO_CACHE1_LITTLE_ENDIAN … #define NV_PFIFO_CACHE1_BIG_ENDIAN … #define NV04_PFIFO_CACHE1_DMA_STATE … #define NV04_PFIFO_CACHE1_DMA_INSTANCE … #define NV04_PFIFO_CACHE1_DMA_CTL … #define NV04_PFIFO_CACHE1_DMA_PUT … #define NV04_PFIFO_CACHE1_DMA_GET … #define NV10_PFIFO_CACHE1_REF_CNT … #define NV10_PFIFO_CACHE1_DMA_SUBROUTINE … #define NV03_PFIFO_CACHE1_PULL0 … #define NV04_PFIFO_CACHE1_PULL0 … #define NV04_PFIFO_CACHE1_PULL0_HASH_FAILED … #define NV04_PFIFO_CACHE1_PULL0_HASH_BUSY … #define NV03_PFIFO_CACHE1_PULL1 … #define NV04_PFIFO_CACHE1_PULL1 … #define NV04_PFIFO_CACHE1_HASH … #define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT … #define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP … #define NV10_PFIFO_CACHE1_ACQUIRE_VALUE … #define NV10_PFIFO_CACHE1_SEMAPHORE … #define NV03_PFIFO_CACHE1_GET … #define NV04_PFIFO_CACHE1_ENGINE … #define NV04_PFIFO_CACHE1_DMA_DCOUNT … #define NV40_PFIFO_GRCTX_INSTANCE … #define NV40_PFIFO_UNK32E4 … #define NV04_PFIFO_CACHE1_METHOD(i) … #define NV04_PFIFO_CACHE1_DATA(i) … #define NV40_PFIFO_CACHE1_METHOD(i) … #define NV40_PFIFO_CACHE1_DATA(i) … #define NV_CRTC0_INTSTAT … #define NV_CRTC0_INTEN … #define NV_CRTC1_INTSTAT … #define NV_CRTC1_INTEN … #define NV_CRTC_INTR_VBLANK … #define NV04_PRAMIN … /* Fifo commands. These are not regs, neither masks */ #define NV03_FIFO_CMD_JUMP … #define NV03_FIFO_CMD_JUMP_OFFSET_MASK … #define NV03_FIFO_CMD_REWIND … /* This is a partial import from rules-ng, a few things may be duplicated. * Eventually we should completely import everything from rules-ng. * For the moment check rules-ng for docs. */ #define NV50_PMC … #define NV50_PMC__LEN … #define NV50_PMC__ESIZE … #define NV50_PMC_BOOT_0 … #define NV50_PMC_BOOT_0_REVISION … #define NV50_PMC_BOOT_0_REVISION__SHIFT … #define NV50_PMC_BOOT_0_ARCH … #define NV50_PMC_BOOT_0_ARCH__SHIFT … #define NV50_PMC_INTR_0 … #define NV50_PMC_INTR_0_PFIFO … #define NV50_PMC_INTR_0_PGRAPH … #define NV50_PMC_INTR_0_PTIMER … #define NV50_PMC_INTR_0_HOTPLUG … #define NV50_PMC_INTR_0_DISPLAY … #define NV50_PMC_INTR_EN_0 … #define NV50_PMC_INTR_EN_0_MASTER … #define NV50_PMC_INTR_EN_0_MASTER_DISABLED … #define NV50_PMC_INTR_EN_0_MASTER_ENABLED … #define NV50_PMC_ENABLE … #define NV50_PMC_ENABLE_PFIFO … #define NV50_PMC_ENABLE_PGRAPH … #define NV50_PCONNECTOR … #define NV50_PCONNECTOR__LEN … #define NV50_PCONNECTOR__ESIZE … #define NV50_PCONNECTOR_HOTPLUG_INTR … #define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C0 … #define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C1 … #define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C2 … #define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C3 … #define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C0 … #define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C1 … #define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C2 … #define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C3 … #define NV50_PCONNECTOR_HOTPLUG_CTRL … #define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C0 … #define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C1 … #define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C2 … #define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C3 … #define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C0 … #define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C1 … #define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C2 … #define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C3 … #define NV50_PCONNECTOR_HOTPLUG_STATE … #define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C0 … #define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C1 … #define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C2 … #define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C3 … #define NV50_PCONNECTOR_I2C_PORT_0 … #define NV50_PCONNECTOR_I2C_PORT_1 … #define NV50_PCONNECTOR_I2C_PORT_2 … #define NV50_PCONNECTOR_I2C_PORT_3 … #define NV50_PCONNECTOR_I2C_PORT_4 … #define NV50_PCONNECTOR_I2C_PORT_5 … #define NV50_AUXCH_DATA_OUT(i, n) … #define NV50_AUXCH_DATA_OUT__SIZE … #define NV50_AUXCH_DATA_IN(i, n) … #define NV50_AUXCH_DATA_IN__SIZE … #define NV50_AUXCH_ADDR(i) … #define NV50_AUXCH_CTRL(i) … #define NV50_AUXCH_CTRL_LINKSTAT … #define NV50_AUXCH_CTRL_LINKSTAT_NOT_READY … #define NV50_AUXCH_CTRL_LINKSTAT_READY … #define NV50_AUXCH_CTRL_LINKEN … #define NV50_AUXCH_CTRL_LINKEN_DISABLED … #define NV50_AUXCH_CTRL_LINKEN_ENABLED … #define NV50_AUXCH_CTRL_EXEC … #define NV50_AUXCH_CTRL_EXEC_COMPLETE … #define NV50_AUXCH_CTRL_EXEC_IN_PROCESS … #define NV50_AUXCH_CTRL_CMD … #define NV50_AUXCH_CTRL_CMD_SHIFT … #define NV50_AUXCH_CTRL_LEN … #define NV50_AUXCH_CTRL_LEN_SHIFT … #define NV50_AUXCH_STAT(i) … #define NV50_AUXCH_STAT_STATE … #define NV50_AUXCH_STAT_STATE_NOT_READY … #define NV50_AUXCH_STAT_STATE_READY … #define NV50_AUXCH_STAT_REPLY … #define NV50_AUXCH_STAT_REPLY_AUX … #define NV50_AUXCH_STAT_REPLY_AUX_ACK … #define NV50_AUXCH_STAT_REPLY_AUX_NACK … #define NV50_AUXCH_STAT_REPLY_AUX_DEFER … #define NV50_AUXCH_STAT_REPLY_I2C … #define NV50_AUXCH_STAT_REPLY_I2C_ACK … #define NV50_AUXCH_STAT_REPLY_I2C_NACK … #define NV50_AUXCH_STAT_REPLY_I2C_DEFER … #define NV50_AUXCH_STAT_COUNT … #define NV50_PBUS … #define NV50_PBUS__LEN … #define NV50_PBUS__ESIZE … #define NV50_PBUS_PCI_ID … #define NV50_PBUS_PCI_ID_VENDOR_ID … #define NV50_PBUS_PCI_ID_VENDOR_ID__SHIFT … #define NV50_PBUS_PCI_ID_DEVICE_ID … #define NV50_PBUS_PCI_ID_DEVICE_ID__SHIFT … #define NV50_PFB … #define NV50_PFB__LEN … #define NV50_PFB__ESIZE … #define NV50_PEXTDEV … #define NV50_PEXTDEV__LEN … #define NV50_PEXTDEV__ESIZE … #define NV50_PROM … #define NV50_PROM__LEN … #define NV50_PROM__ESIZE … #define NV50_PGRAPH … #define NV50_PGRAPH__LEN … #define NV50_PGRAPH__ESIZE … #define NV50_PDISPLAY … #define NV50_PDISPLAY_OBJECTS … #define NV50_PDISPLAY_INTR_0 … #define NV50_PDISPLAY_INTR_1 … #define NV50_PDISPLAY_INTR_1_VBLANK_CRTC … #define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_SHIFT … #define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(n) … #define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0 … #define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1 … #define NV50_PDISPLAY_INTR_1_CLK_UNK10 … #define NV50_PDISPLAY_INTR_1_CLK_UNK20 … #define NV50_PDISPLAY_INTR_1_CLK_UNK40 … #define NV50_PDISPLAY_INTR_EN_0 … #define NV50_PDISPLAY_INTR_EN_1 … #define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC … #define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_(n) … #define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_0 … #define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_1 … #define NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 … #define NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 … #define NV50_PDISPLAY_INTR_EN_1_CLK_UNK40 … #define NV50_PDISPLAY_UNK30_CTRL … #define NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK0 … #define NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK1 … #define NV50_PDISPLAY_UNK30_CTRL_PENDING … #define NV50_PDISPLAY_TRAPPED_ADDR(i) … #define NV50_PDISPLAY_TRAPPED_DATA(i) … #define NV50_PDISPLAY_EVO_CTRL(i) … #define NV50_PDISPLAY_EVO_CTRL_DMA … #define NV50_PDISPLAY_EVO_CTRL_DMA_DISABLED … #define NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED … #define NV50_PDISPLAY_EVO_DMA_CB(i) … #define NV50_PDISPLAY_EVO_DMA_CB_LOCATION … #define NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM … #define NV50_PDISPLAY_EVO_DMA_CB_LOCATION_SYSTEM … #define NV50_PDISPLAY_EVO_DMA_CB_VALID … #define NV50_PDISPLAY_EVO_UNK2(i) … #define NV50_PDISPLAY_EVO_HASH_TAG(i) … #define NV50_PDISPLAY_CURSOR … #define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i) … #define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON … #define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS … #define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE … #define NV50_PDISPLAY_PIO_CTRL … #define NV50_PDISPLAY_PIO_CTRL_PENDING … #define NV50_PDISPLAY_PIO_CTRL_MTHD … #define NV50_PDISPLAY_PIO_CTRL_ENABLED … #define NV50_PDISPLAY_PIO_DATA … #define NV50_PDISPLAY_CRTC_P(i, r) … #define NV50_PDISPLAY_CRTC_C(i, r) … #define NV50_PDISPLAY_CRTC_UNK_0A18 … #define NV50_PDISPLAY_CRTC_CLUT_MODE … #define NV50_PDISPLAY_CRTC_INTERLACE … #define NV50_PDISPLAY_CRTC_SCALE_CTRL … #define NV50_PDISPLAY_CRTC_CURSOR_CTRL … #define NV50_PDISPLAY_CRTC_UNK0A78 … #define NV50_PDISPLAY_CRTC_UNK0AB8 … #define NV50_PDISPLAY_CRTC_DEPTH … #define NV50_PDISPLAY_CRTC_CLOCK … #define NV50_PDISPLAY_CRTC_COLOR_CTRL … #define NV50_PDISPLAY_CRTC_SYNC_START_TO_BLANK_END … #define NV50_PDISPLAY_CRTC_MODE_UNK1 … #define NV50_PDISPLAY_CRTC_DISPLAY_TOTAL … #define NV50_PDISPLAY_CRTC_SYNC_DURATION … #define NV50_PDISPLAY_CRTC_MODE_UNK2 … #define NV50_PDISPLAY_CRTC_UNK_0B10 … #define NV50_PDISPLAY_CRTC_FB_SIZE … #define NV50_PDISPLAY_CRTC_FB_PITCH … #define NV50_PDISPLAY_CRTC_FB_PITCH_LINEAR … #define NV50_PDISPLAY_CRTC_FB_POS … #define NV50_PDISPLAY_CRTC_SCALE_CENTER_OFFSET … #define NV50_PDISPLAY_CRTC_REAL_RES … #define NV50_PDISPLAY_CRTC_SCALE_RES1 … #define NV50_PDISPLAY_CRTC_SCALE_RES2 … #define NV50_PDISPLAY_DAC_MODE_CTRL_P(i) … #define NV50_PDISPLAY_DAC_MODE_CTRL_C(i) … #define NV50_PDISPLAY_SOR_MODE_CTRL_P(i) … #define NV50_PDISPLAY_SOR_MODE_CTRL_C(i) … #define NV50_PDISPLAY_EXT_MODE_CTRL_P(i) … #define NV50_PDISPLAY_EXT_MODE_CTRL_C(i) … #define NV50_PDISPLAY_DAC_MODE_CTRL2_P(i) … #define NV50_PDISPLAY_DAC_MODE_CTRL2_C(i) … #define NV90_PDISPLAY_SOR_MODE_CTRL_P(i) … #define NV90_PDISPLAY_SOR_MODE_CTRL_C(i) … #define NV50_PDISPLAY_CRTC_CLK … #define NV50_PDISPLAY_CRTC_CLK_CTRL1(i) … #define NV50_PDISPLAY_CRTC_CLK_CTRL1_CONNECTED … #define NV50_PDISPLAY_CRTC_CLK_VPLL_A(i) … #define NV50_PDISPLAY_CRTC_CLK_VPLL_B(i) … #define NV50_PDISPLAY_CRTC_CLK_CTRL2(i) … #define NV50_PDISPLAY_DAC_CLK … #define NV50_PDISPLAY_DAC_CLK_CTRL2(i) … #define NV50_PDISPLAY_SOR_CLK … #define NV50_PDISPLAY_SOR_CLK_CTRL2(i) … #define NV50_PDISPLAY_VGACRTC(r) … #define NV50_PDISPLAY_DAC … #define NV50_PDISPLAY_DAC_DPMS_CTRL(i) … #define NV50_PDISPLAY_DAC_DPMS_CTRL_HSYNC_OFF … #define NV50_PDISPLAY_DAC_DPMS_CTRL_VSYNC_OFF … #define NV50_PDISPLAY_DAC_DPMS_CTRL_BLANKED … #define NV50_PDISPLAY_DAC_DPMS_CTRL_OFF … #define NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING … #define NV50_PDISPLAY_DAC_LOAD_CTRL(i) … #define NV50_PDISPLAY_DAC_LOAD_CTRL_ACTIVE … #define NV50_PDISPLAY_DAC_LOAD_CTRL_PRESENT … #define NV50_PDISPLAY_DAC_LOAD_CTRL_DONE … #define NV50_PDISPLAY_DAC_CLK_CTRL1(i) … #define NV50_PDISPLAY_DAC_CLK_CTRL1_CONNECTED … #define NV50_PDISPLAY_SOR … #define NV50_PDISPLAY_SOR_DPMS_CTRL(i) … #define NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING … #define NV50_PDISPLAY_SOR_DPMS_CTRL_ON … #define NV50_PDISPLAY_SOR_CLK_CTRL1(i) … #define NV50_PDISPLAY_SOR_CLK_CTRL1_CONNECTED … #define NV50_PDISPLAY_SOR_DPMS_STATE(i) … #define NV50_PDISPLAY_SOR_DPMS_STATE_ACTIVE … #define NV50_PDISPLAY_SOR_DPMS_STATE_BLANKED … #define NV50_PDISPLAY_SOR_DPMS_STATE_WAIT … #define NV50_PDISP_SOR_PWM_DIV(i) … #define NV50_PDISP_SOR_PWM_CTL(i) … #define NV50_PDISP_SOR_PWM_CTL_NEW … #define NVA3_PDISP_SOR_PWM_CTL_UNK … #define NV50_PDISP_SOR_PWM_CTL_VAL … #define NVA3_PDISP_SOR_PWM_CTL_VAL … #define NV50_SOR_DP_CTRL(i, l) … #define NV50_SOR_DP_CTRL_ENABLED … #define NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED … #define NV50_SOR_DP_CTRL_LANE_MASK … #define NV50_SOR_DP_CTRL_LANE_0_ENABLED … #define NV50_SOR_DP_CTRL_LANE_1_ENABLED … #define NV50_SOR_DP_CTRL_LANE_2_ENABLED … #define NV50_SOR_DP_CTRL_LANE_3_ENABLED … #define NV50_SOR_DP_CTRL_TRAINING_PATTERN … #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_DISABLED … #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_1 … #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_2 … #define NV50_SOR_DP_UNK118(i, l) … #define NV50_SOR_DP_UNK120(i, l) … #define NV50_SOR_DP_SCFG(i, l) … #define NV50_SOR_DP_UNK130(i, l) … #define NV50_PDISPLAY_USER(i) … #define NV50_PDISPLAY_USER_PUT(i) … #define NV50_PDISPLAY_USER_GET(i) … #define NV50_PDISPLAY_CURSOR_USER … #define NV50_PDISPLAY_CURSOR_USER_POS_CTRL(i) … #define NV50_PDISPLAY_CURSOR_USER_POS(i) …
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