/* SPDX-License-Identifier: GPL-2.0-only */ /* drivers/gpu/drm/exynos/regs-fimc.h * * Copyright (c) 2012 Samsung Electronics Co., Ltd. * http://www.samsung.com/ * * Register definition file for Samsung Camera Interface (FIMC) driver */ #ifndef EXYNOS_REGS_FIMC_H #define EXYNOS_REGS_FIMC_H /* * Register part */ /* Input source format */ #define EXYNOS_CISRCFMT … /* Window offset */ #define EXYNOS_CIWDOFST … /* Global control */ #define EXYNOS_CIGCTRL … /* Window offset 2 */ #define EXYNOS_CIWDOFST2 … /* Y 1st frame start address for output DMA */ #define EXYNOS_CIOYSA1 … /* Y 2nd frame start address for output DMA */ #define EXYNOS_CIOYSA2 … /* Y 3rd frame start address for output DMA */ #define EXYNOS_CIOYSA3 … /* Y 4th frame start address for output DMA */ #define EXYNOS_CIOYSA4 … /* Cb 1st frame start address for output DMA */ #define EXYNOS_CIOCBSA1 … /* Cb 2nd frame start address for output DMA */ #define EXYNOS_CIOCBSA2 … /* Cb 3rd frame start address for output DMA */ #define EXYNOS_CIOCBSA3 … /* Cb 4th frame start address for output DMA */ #define EXYNOS_CIOCBSA4 … /* Cr 1st frame start address for output DMA */ #define EXYNOS_CIOCRSA1 … /* Cr 2nd frame start address for output DMA */ #define EXYNOS_CIOCRSA2 … /* Cr 3rd frame start address for output DMA */ #define EXYNOS_CIOCRSA3 … /* Cr 4th frame start address for output DMA */ #define EXYNOS_CIOCRSA4 … /* Target image format */ #define EXYNOS_CITRGFMT … /* Output DMA control */ #define EXYNOS_CIOCTRL … /* Pre-scaler control 1 */ #define EXYNOS_CISCPRERATIO … /* Pre-scaler control 2 */ #define EXYNOS_CISCPREDST … /* Main scaler control */ #define EXYNOS_CISCCTRL … /* Target area */ #define EXYNOS_CITAREA … /* Status */ #define EXYNOS_CISTATUS … /* Status2 */ #define EXYNOS_CISTATUS2 … /* Image capture enable command */ #define EXYNOS_CIIMGCPT … /* Capture sequence */ #define EXYNOS_CICPTSEQ … /* Image effects */ #define EXYNOS_CIIMGEFF … /* Y frame start address for input DMA */ #define EXYNOS_CIIYSA0 … /* Cb frame start address for input DMA */ #define EXYNOS_CIICBSA0 … /* Cr frame start address for input DMA */ #define EXYNOS_CIICRSA0 … /* Input DMA Y Line Skip */ #define EXYNOS_CIILINESKIP_Y … /* Input DMA Cb Line Skip */ #define EXYNOS_CIILINESKIP_CB … /* Input DMA Cr Line Skip */ #define EXYNOS_CIILINESKIP_CR … /* Real input DMA image size */ #define EXYNOS_CIREAL_ISIZE … /* Input DMA control */ #define EXYNOS_MSCTRL … /* Y frame start address for input DMA */ #define EXYNOS_CIIYSA1 … /* Cb frame start address for input DMA */ #define EXYNOS_CIICBSA1 … /* Cr frame start address for input DMA */ #define EXYNOS_CIICRSA1 … /* Output DMA Y offset */ #define EXYNOS_CIOYOFF … /* Output DMA CB offset */ #define EXYNOS_CIOCBOFF … /* Output DMA CR offset */ #define EXYNOS_CIOCROFF … /* Input DMA Y offset */ #define EXYNOS_CIIYOFF … /* Input DMA CB offset */ #define EXYNOS_CIICBOFF … /* Input DMA CR offset */ #define EXYNOS_CIICROFF … /* Input DMA original image size */ #define EXYNOS_ORGISIZE … /* Output DMA original image size */ #define EXYNOS_ORGOSIZE … /* Real output DMA image size */ #define EXYNOS_CIEXTEN … /* DMA parameter */ #define EXYNOS_CIDMAPARAM … /* MIPI CSI image format */ #define EXYNOS_CSIIMGFMT … /* FIMC Clock Source Select */ #define EXYNOS_MISC_FIMC … /* Add for FIMC v5.1 */ /* Output Frame Buffer Sequence */ #define EXYNOS_CIFCNTSEQ … /* Y 5th frame start address for output DMA */ #define EXYNOS_CIOYSA5 … /* Y 6th frame start address for output DMA */ #define EXYNOS_CIOYSA6 … /* Y 7th frame start address for output DMA */ #define EXYNOS_CIOYSA7 … /* Y 8th frame start address for output DMA */ #define EXYNOS_CIOYSA8 … /* Y 9th frame start address for output DMA */ #define EXYNOS_CIOYSA9 … /* Y 10th frame start address for output DMA */ #define EXYNOS_CIOYSA10 … /* Y 11th frame start address for output DMA */ #define EXYNOS_CIOYSA11 … /* Y 12th frame start address for output DMA */ #define EXYNOS_CIOYSA12 … /* Y 13th frame start address for output DMA */ #define EXYNOS_CIOYSA13 … /* Y 14th frame start address for output DMA */ #define EXYNOS_CIOYSA14 … /* Y 15th frame start address for output DMA */ #define EXYNOS_CIOYSA15 … /* Y 16th frame start address for output DMA */ #define EXYNOS_CIOYSA16 … /* Y 17th frame start address for output DMA */ #define EXYNOS_CIOYSA17 … /* Y 18th frame start address for output DMA */ #define EXYNOS_CIOYSA18 … /* Y 19th frame start address for output DMA */ #define EXYNOS_CIOYSA19 … /* Y 20th frame start address for output DMA */ #define EXYNOS_CIOYSA20 … /* Y 21th frame start address for output DMA */ #define EXYNOS_CIOYSA21 … /* Y 22th frame start address for output DMA */ #define EXYNOS_CIOYSA22 … /* Y 23th frame start address for output DMA */ #define EXYNOS_CIOYSA23 … /* Y 24th frame start address for output DMA */ #define EXYNOS_CIOYSA24 … /* Y 25th frame start address for output DMA */ #define EXYNOS_CIOYSA25 … /* Y 26th frame start address for output DMA */ #define EXYNOS_CIOYSA26 … /* Y 27th frame start address for output DMA */ #define EXYNOS_CIOYSA27 … /* Y 28th frame start address for output DMA */ #define EXYNOS_CIOYSA28 … /* Y 29th frame start address for output DMA */ #define EXYNOS_CIOYSA29 … /* Y 30th frame start address for output DMA */ #define EXYNOS_CIOYSA30 … /* Y 31th frame start address for output DMA */ #define EXYNOS_CIOYSA31 … /* Y 32th frame start address for output DMA */ #define EXYNOS_CIOYSA32 … /* CB 5th frame start address for output DMA */ #define EXYNOS_CIOCBSA5 … /* CB 6th frame start address for output DMA */ #define EXYNOS_CIOCBSA6 … /* CB 7th frame start address for output DMA */ #define EXYNOS_CIOCBSA7 … /* CB 8th frame start address for output DMA */ #define EXYNOS_CIOCBSA8 … /* CB 9th frame start address for output DMA */ #define EXYNOS_CIOCBSA9 … /* CB 10th frame start address for output DMA */ #define EXYNOS_CIOCBSA10 … /* CB 11th frame start address for output DMA */ #define EXYNOS_CIOCBSA11 … /* CB 12th frame start address for output DMA */ #define EXYNOS_CIOCBSA12 … /* CB 13th frame start address for output DMA */ #define EXYNOS_CIOCBSA13 … /* CB 14th frame start address for output DMA */ #define EXYNOS_CIOCBSA14 … /* CB 15th frame start address for output DMA */ #define EXYNOS_CIOCBSA15 … /* CB 16th frame start address for output DMA */ #define EXYNOS_CIOCBSA16 … /* CB 17th frame start address for output DMA */ #define EXYNOS_CIOCBSA17 … /* CB 18th frame start address for output DMA */ #define EXYNOS_CIOCBSA18 … /* CB 19th frame start address for output DMA */ #define EXYNOS_CIOCBSA19 … /* CB 20th frame start address for output DMA */ #define EXYNOS_CIOCBSA20 … /* CB 21th frame start address for output DMA */ #define EXYNOS_CIOCBSA21 … /* CB 22th frame start address for output DMA */ #define EXYNOS_CIOCBSA22 … /* CB 23th frame start address for output DMA */ #define EXYNOS_CIOCBSA23 … /* CB 24th frame start address for output DMA */ #define EXYNOS_CIOCBSA24 … /* CB 25th frame start address for output DMA */ #define EXYNOS_CIOCBSA25 … /* CB 26th frame start address for output DMA */ #define EXYNOS_CIOCBSA26 … /* CB 27th frame start address for output DMA */ #define EXYNOS_CIOCBSA27 … /* CB 28th frame start address for output DMA */ #define EXYNOS_CIOCBSA28 … /* CB 29th frame start address for output DMA */ #define EXYNOS_CIOCBSA29 … /* CB 30th frame start address for output DMA */ #define EXYNOS_CIOCBSA30 … /* CB 31th frame start address for output DMA */ #define EXYNOS_CIOCBSA31 … /* CB 32th frame start address for output DMA */ #define EXYNOS_CIOCBSA32 … /* CR 5th frame start address for output DMA */ #define EXYNOS_CIOCRSA5 … /* CR 6th frame start address for output DMA */ #define EXYNOS_CIOCRSA6 … /* CR 7th frame start address for output DMA */ #define EXYNOS_CIOCRSA7 … /* CR 8th frame start address for output DMA */ #define EXYNOS_CIOCRSA8 … /* CR 9th frame start address for output DMA */ #define EXYNOS_CIOCRSA9 … /* CR 10th frame start address for output DMA */ #define EXYNOS_CIOCRSA10 … /* CR 11th frame start address for output DMA */ #define EXYNOS_CIOCRSA11 … /* CR 12th frame start address for output DMA */ #define EXYNOS_CIOCRSA12 … /* CR 13th frame start address for output DMA */ #define EXYNOS_CIOCRSA13 … /* CR 14th frame start address for output DMA */ #define EXYNOS_CIOCRSA14 … /* CR 15th frame start address for output DMA */ #define EXYNOS_CIOCRSA15 … /* CR 16th frame start address for output DMA */ #define EXYNOS_CIOCRSA16 … /* CR 17th frame start address for output DMA */ #define EXYNOS_CIOCRSA17 … /* CR 18th frame start address for output DMA */ #define EXYNOS_CIOCRSA18 … /* CR 19th frame start address for output DMA */ #define EXYNOS_CIOCRSA19 … /* CR 20th frame start address for output DMA */ #define EXYNOS_CIOCRSA20 … /* CR 21th frame start address for output DMA */ #define EXYNOS_CIOCRSA21 … /* CR 22th frame start address for output DMA */ #define EXYNOS_CIOCRSA22 … /* CR 23th frame start address for output DMA */ #define EXYNOS_CIOCRSA23 … /* CR 24th frame start address for output DMA */ #define EXYNOS_CIOCRSA24 … /* CR 25th frame start address for output DMA */ #define EXYNOS_CIOCRSA25 … /* CR 26th frame start address for output DMA */ #define EXYNOS_CIOCRSA26 … /* CR 27th frame start address for output DMA */ #define EXYNOS_CIOCRSA27 … /* CR 28th frame start address for output DMA */ #define EXYNOS_CIOCRSA28 … /* CR 29th frame start address for output DMA */ #define EXYNOS_CIOCRSA29 … /* CR 30th frame start address for output DMA */ #define EXYNOS_CIOCRSA30 … /* CR 31th frame start address for output DMA */ #define EXYNOS_CIOCRSA31 … /* CR 32th frame start address for output DMA */ #define EXYNOS_CIOCRSA32 … /* * Macro part */ /* frame start address 1 ~ 4, 5 ~ 32 */ /* Number of Default PingPong Memory */ #define DEF_PP … #define EXYNOS_CIOYSA(__x) … #define EXYNOS_CIOCBSA(__x) … #define EXYNOS_CIOCRSA(__x) … /* Number of Default PingPong Memory */ #define DEF_IPP … #define EXYNOS_CIIYSA(__x) … #define EXYNOS_CIICBSA(__x) … #define EXYNOS_CIICRSA(__x) … #define EXYNOS_CISRCFMT_SOURCEHSIZE(x) … #define EXYNOS_CISRCFMT_SOURCEVSIZE(x) … #define EXYNOS_CIWDOFST_WINHOROFST(x) … #define EXYNOS_CIWDOFST_WINVEROFST(x) … #define EXYNOS_CIWDOFST2_WINHOROFST2(x) … #define EXYNOS_CIWDOFST2_WINVEROFST2(x) … #define EXYNOS_CITRGFMT_TARGETHSIZE(x) … #define EXYNOS_CITRGFMT_TARGETVSIZE(x) … #define EXYNOS_CISCPRERATIO_SHFACTOR(x) … #define EXYNOS_CISCPRERATIO_PREHORRATIO(x) … #define EXYNOS_CISCPRERATIO_PREVERRATIO(x) … #define EXYNOS_CISCPREDST_PREDSTWIDTH(x) … #define EXYNOS_CISCPREDST_PREDSTHEIGHT(x) … #define EXYNOS_CISCCTRL_MAINHORRATIO(x) … #define EXYNOS_CISCCTRL_MAINVERRATIO(x) … #define EXYNOS_CITAREA_TARGET_AREA(x) … #define EXYNOS_CISTATUS_GET_FRAME_COUNT(x) … #define EXYNOS_CISTATUS_GET_FRAME_END(x) … #define EXYNOS_CISTATUS_GET_LAST_CAPTURE_END(x) … #define EXYNOS_CISTATUS_GET_LCD_STATUS(x) … #define EXYNOS_CISTATUS_GET_ENVID_STATUS(x) … #define EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(x) … #define EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(x) … #define EXYNOS_CIIMGEFF_FIN(x) … #define EXYNOS_CIIMGEFF_PAT_CB(x) … #define EXYNOS_CIIMGEFF_PAT_CR(x) … #define EXYNOS_CIILINESKIP(x) … #define EXYNOS_CIREAL_ISIZE_HEIGHT(x) … #define EXYNOS_CIREAL_ISIZE_WIDTH(x) … #define EXYNOS_MSCTRL_SUCCESSIVE_COUNT(x) … #define EXYNOS_MSCTRL_GET_INDMA_STATUS(x) … #define EXYNOS_CIOYOFF_VERTICAL(x) … #define EXYNOS_CIOYOFF_HORIZONTAL(x) … #define EXYNOS_CIOCBOFF_VERTICAL(x) … #define EXYNOS_CIOCBOFF_HORIZONTAL(x) … #define EXYNOS_CIOCROFF_VERTICAL(x) … #define EXYNOS_CIOCROFF_HORIZONTAL(x) … #define EXYNOS_CIIYOFF_VERTICAL(x) … #define EXYNOS_CIIYOFF_HORIZONTAL(x) … #define EXYNOS_CIICBOFF_VERTICAL(x) … #define EXYNOS_CIICBOFF_HORIZONTAL(x) … #define EXYNOS_CIICROFF_VERTICAL(x) … #define EXYNOS_CIICROFF_HORIZONTAL(x) … #define EXYNOS_ORGISIZE_VERTICAL(x) … #define EXYNOS_ORGISIZE_HORIZONTAL(x) … #define EXYNOS_ORGOSIZE_VERTICAL(x) … #define EXYNOS_ORGOSIZE_HORIZONTAL(x) … #define EXYNOS_CIEXTEN_TARGETH_EXT(x) … #define EXYNOS_CIEXTEN_TARGETV_EXT(x) … #define EXYNOS_CIEXTEN_MAINHORRATIO_EXT(x) … #define EXYNOS_CIEXTEN_MAINVERRATIO_EXT(x) … /* * Bit definition part */ /* Source format register */ #define EXYNOS_CISRCFMT_ITU601_8BIT … #define EXYNOS_CISRCFMT_ITU656_8BIT … #define EXYNOS_CISRCFMT_ITU601_16BIT … #define EXYNOS_CISRCFMT_ORDER422_YCBYCR … #define EXYNOS_CISRCFMT_ORDER422_YCRYCB … #define EXYNOS_CISRCFMT_ORDER422_CBYCRY … #define EXYNOS_CISRCFMT_ORDER422_CRYCBY … /* ITU601 16bit only */ #define EXYNOS_CISRCFMT_ORDER422_Y4CBCRCBCR … /* ITU601 16bit only */ #define EXYNOS_CISRCFMT_ORDER422_Y4CRCBCRCB … /* Window offset register */ #define EXYNOS_CIWDOFST_WINOFSEN … #define EXYNOS_CIWDOFST_CLROVFIY … #define EXYNOS_CIWDOFST_CLROVRLB … #define EXYNOS_CIWDOFST_WINHOROFST_MASK … #define EXYNOS_CIWDOFST_CLROVFICB … #define EXYNOS_CIWDOFST_CLROVFICR … #define EXYNOS_CIWDOFST_WINVEROFST_MASK … /* Global control register */ #define EXYNOS_CIGCTRL_SWRST … #define EXYNOS_CIGCTRL_CAMRST_A … #define EXYNOS_CIGCTRL_SELCAM_ITU_B … #define EXYNOS_CIGCTRL_SELCAM_ITU_A … #define EXYNOS_CIGCTRL_SELCAM_ITU_MASK … #define EXYNOS_CIGCTRL_TESTPATTERN_NORMAL … #define EXYNOS_CIGCTRL_TESTPATTERN_COLOR_BAR … #define EXYNOS_CIGCTRL_TESTPATTERN_HOR_INC … #define EXYNOS_CIGCTRL_TESTPATTERN_VER_INC … #define EXYNOS_CIGCTRL_TESTPATTERN_MASK … #define EXYNOS_CIGCTRL_TESTPATTERN_SHIFT … #define EXYNOS_CIGCTRL_INVPOLPCLK … #define EXYNOS_CIGCTRL_INVPOLVSYNC … #define EXYNOS_CIGCTRL_INVPOLHREF … #define EXYNOS_CIGCTRL_IRQ_OVFEN … #define EXYNOS_CIGCTRL_HREF_MASK … #define EXYNOS_CIGCTRL_IRQ_EDGE … #define EXYNOS_CIGCTRL_IRQ_LEVEL … #define EXYNOS_CIGCTRL_IRQ_CLR … #define EXYNOS_CIGCTRL_IRQ_END_DISABLE … #define EXYNOS_CIGCTRL_IRQ_DISABLE … #define EXYNOS_CIGCTRL_IRQ_ENABLE … #define EXYNOS_CIGCTRL_SHADOW_DISABLE … #define EXYNOS_CIGCTRL_CAM_JPEG … #define EXYNOS_CIGCTRL_SELCAM_MIPI_B … #define EXYNOS_CIGCTRL_SELCAM_MIPI_A … #define EXYNOS_CIGCTRL_SELCAM_MIPI_MASK … #define EXYNOS_CIGCTRL_SELWB_CAMIF_CAMERA … #define EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK … #define EXYNOS_CIGCTRL_SELWRITEBACK_MASK … #define EXYNOS_CIGCTRL_SELWRITEBACK_A … #define EXYNOS_CIGCTRL_SELWRITEBACK_B … #define EXYNOS_CIGCTRL_SELWB_CAMIF_MASK … #define EXYNOS_CIGCTRL_CSC_ITU601 … #define EXYNOS_CIGCTRL_CSC_ITU709 … #define EXYNOS_CIGCTRL_CSC_MASK … #define EXYNOS_CIGCTRL_INVPOLHSYNC … #define EXYNOS_CIGCTRL_SELCAM_FIMC_ITU … #define EXYNOS_CIGCTRL_SELCAM_FIMC_MIPI … #define EXYNOS_CIGCTRL_SELCAM_FIMC_MASK … #define EXYNOS_CIGCTRL_PROGRESSIVE … #define EXYNOS_CIGCTRL_INTERLACE … /* Window offset2 register */ #define EXYNOS_CIWDOFST_WINHOROFST2_MASK … #define EXYNOS_CIWDOFST_WINVEROFST2_MASK … /* Target format register */ #define EXYNOS_CITRGFMT_INROT90_CLOCKWISE … #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420 … #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422 … #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE … #define EXYNOS_CITRGFMT_OUTFORMAT_RGB … #define EXYNOS_CITRGFMT_OUTFORMAT_MASK … #define EXYNOS_CITRGFMT_FLIP_SHIFT … #define EXYNOS_CITRGFMT_FLIP_NORMAL … #define EXYNOS_CITRGFMT_FLIP_X_MIRROR … #define EXYNOS_CITRGFMT_FLIP_Y_MIRROR … #define EXYNOS_CITRGFMT_FLIP_180 … #define EXYNOS_CITRGFMT_FLIP_MASK … #define EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE … #define EXYNOS_CITRGFMT_TARGETV_MASK … #define EXYNOS_CITRGFMT_TARGETH_MASK … /* Output DMA control register */ #define EXYNOS_CIOCTRL_WEAVE_OUT … #define EXYNOS_CIOCTRL_WEAVE_MASK … #define EXYNOS_CIOCTRL_LASTENDEN … #define EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR … #define EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB … #define EXYNOS_CIOCTRL_ORDER2P_MSB_CRCB … #define EXYNOS_CIOCTRL_ORDER2P_MSB_CBCR … #define EXYNOS_CIOCTRL_ORDER2P_SHIFT … #define EXYNOS_CIOCTRL_ORDER2P_MASK … #define EXYNOS_CIOCTRL_YCBCR_3PLANE … #define EXYNOS_CIOCTRL_YCBCR_2PLANE … #define EXYNOS_CIOCTRL_YCBCR_PLANE_MASK … #define EXYNOS_CIOCTRL_LASTIRQ_ENABLE … #define EXYNOS_CIOCTRL_ALPHA_OUT … #define EXYNOS_CIOCTRL_ORDER422_YCBYCR … #define EXYNOS_CIOCTRL_ORDER422_YCRYCB … #define EXYNOS_CIOCTRL_ORDER422_CBYCRY … #define EXYNOS_CIOCTRL_ORDER422_CRYCBY … #define EXYNOS_CIOCTRL_ORDER422_MASK … /* Main scaler control register */ #define EXYNOS_CISCCTRL_SCALERBYPASS … #define EXYNOS_CISCCTRL_SCALEUP_H … #define EXYNOS_CISCCTRL_SCALEUP_V … #define EXYNOS_CISCCTRL_CSCR2Y_NARROW … #define EXYNOS_CISCCTRL_CSCR2Y_WIDE … #define EXYNOS_CISCCTRL_CSCY2R_NARROW … #define EXYNOS_CISCCTRL_CSCY2R_WIDE … #define EXYNOS_CISCCTRL_LCDPATHEN_FIFO … #define EXYNOS_CISCCTRL_PROGRESSIVE … #define EXYNOS_CISCCTRL_INTERLACE … #define EXYNOS_CISCCTRL_SCAN_MASK … #define EXYNOS_CISCCTRL_SCALERSTART … #define EXYNOS_CISCCTRL_INRGB_FMT_RGB565 … #define EXYNOS_CISCCTRL_INRGB_FMT_RGB666 … #define EXYNOS_CISCCTRL_INRGB_FMT_RGB888 … #define EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK … #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565 … #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB666 … #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 … #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK … #define EXYNOS_CISCCTRL_EXTRGB_NORMAL … #define EXYNOS_CISCCTRL_EXTRGB_EXTENSION … #define EXYNOS_CISCCTRL_ONE2ONE … #define EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK … #define EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK … /* Status register */ #define EXYNOS_CISTATUS_OVFIY … #define EXYNOS_CISTATUS_OVFICB … #define EXYNOS_CISTATUS_OVFICR … #define EXYNOS_CISTATUS_VSYNC … #define EXYNOS_CISTATUS_SCALERSTART … #define EXYNOS_CISTATUS_WINOFSTEN … #define EXYNOS_CISTATUS_IMGCPTEN … #define EXYNOS_CISTATUS_IMGCPTENSC … #define EXYNOS_CISTATUS_VSYNC_A … #define EXYNOS_CISTATUS_VSYNC_B … #define EXYNOS_CISTATUS_OVRLB … #define EXYNOS_CISTATUS_FRAMEEND … #define EXYNOS_CISTATUS_LASTCAPTUREEND … #define EXYNOS_CISTATUS_VVALID_A … #define EXYNOS_CISTATUS_VVALID_B … /* Image capture enable register */ #define EXYNOS_CIIMGCPT_IMGCPTEN … #define EXYNOS_CIIMGCPT_IMGCPTEN_SC … #define EXYNOS_CIIMGCPT_CPT_FREN_ENABLE … #define EXYNOS_CIIMGCPT_CPT_FRMOD_EN … #define EXYNOS_CIIMGCPT_CPT_FRMOD_CNT … /* Image effects register */ #define EXYNOS_CIIMGEFF_IE_DISABLE … #define EXYNOS_CIIMGEFF_IE_ENABLE … #define EXYNOS_CIIMGEFF_IE_SC_BEFORE … #define EXYNOS_CIIMGEFF_IE_SC_AFTER … #define EXYNOS_CIIMGEFF_FIN_BYPASS … #define EXYNOS_CIIMGEFF_FIN_ARBITRARY … #define EXYNOS_CIIMGEFF_FIN_NEGATIVE … #define EXYNOS_CIIMGEFF_FIN_ARTFREEZE … #define EXYNOS_CIIMGEFF_FIN_EMBOSSING … #define EXYNOS_CIIMGEFF_FIN_SILHOUETTE … #define EXYNOS_CIIMGEFF_FIN_MASK … #define EXYNOS_CIIMGEFF_PAT_CBCR_MASK … /* Real input DMA size register */ #define EXYNOS_CIREAL_ISIZE_AUTOLOAD_ENABLE … #define EXYNOS_CIREAL_ISIZE_ADDR_CH_DISABLE … #define EXYNOS_CIREAL_ISIZE_HEIGHT_MASK … #define EXYNOS_CIREAL_ISIZE_WIDTH_MASK … /* Input DMA control register */ #define EXYNOS_MSCTRL_FIELD_MASK … #define EXYNOS_MSCTRL_FIELD_WEAVE … #define EXYNOS_MSCTRL_FIELD_NORMAL … #define EXYNOS_MSCTRL_BURST_CNT … #define EXYNOS_MSCTRL_BURST_CNT_MASK … #define EXYNOS_MSCTRL_ORDER2P_LSB_CBCR … #define EXYNOS_MSCTRL_ORDER2P_LSB_CRCB … #define EXYNOS_MSCTRL_ORDER2P_MSB_CRCB … #define EXYNOS_MSCTRL_ORDER2P_MSB_CBCR … #define EXYNOS_MSCTRL_ORDER2P_SHIFT … #define EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK … #define EXYNOS_MSCTRL_C_INT_IN_3PLANE … #define EXYNOS_MSCTRL_C_INT_IN_2PLANE … #define EXYNOS_MSCTRL_FLIP_SHIFT … #define EXYNOS_MSCTRL_FLIP_NORMAL … #define EXYNOS_MSCTRL_FLIP_X_MIRROR … #define EXYNOS_MSCTRL_FLIP_Y_MIRROR … #define EXYNOS_MSCTRL_FLIP_180 … #define EXYNOS_MSCTRL_FLIP_MASK … #define EXYNOS_MSCTRL_ORDER422_CRYCBY … #define EXYNOS_MSCTRL_ORDER422_YCRYCB … #define EXYNOS_MSCTRL_ORDER422_CBYCRY … #define EXYNOS_MSCTRL_ORDER422_YCBYCR … #define EXYNOS_MSCTRL_INPUT_EXTCAM … #define EXYNOS_MSCTRL_INPUT_MEMORY … #define EXYNOS_MSCTRL_INPUT_MASK … #define EXYNOS_MSCTRL_INFORMAT_YCBCR420 … #define EXYNOS_MSCTRL_INFORMAT_YCBCR422 … #define EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE … #define EXYNOS_MSCTRL_INFORMAT_RGB … #define EXYNOS_MSCTRL_ENVID … /* DMA parameter register */ #define EXYNOS_CIDMAPARAM_R_MODE_LINEAR … #define EXYNOS_CIDMAPARAM_R_MODE_CONFTILE … #define EXYNOS_CIDMAPARAM_R_MODE_16X16 … #define EXYNOS_CIDMAPARAM_R_MODE_64X32 … #define EXYNOS_CIDMAPARAM_R_MODE_MASK … #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_64 … #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_128 … #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_256 … #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_512 … #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_1024 … #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_2048 … #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_4096 … #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_1 … #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_2 … #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_4 … #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_8 … #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_16 … #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_32 … #define EXYNOS_CIDMAPARAM_W_MODE_LINEAR … #define EXYNOS_CIDMAPARAM_W_MODE_CONFTILE … #define EXYNOS_CIDMAPARAM_W_MODE_16X16 … #define EXYNOS_CIDMAPARAM_W_MODE_64X32 … #define EXYNOS_CIDMAPARAM_W_MODE_MASK … #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_64 … #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_128 … #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_256 … #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_512 … #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_1024 … #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_2048 … #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_4096 … #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_1 … #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_2 … #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_4 … #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_8 … #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_16 … #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_32 … /* Gathering Extension register */ #define EXYNOS_CIEXTEN_TARGETH_EXT_MASK … #define EXYNOS_CIEXTEN_TARGETV_EXT_MASK … #define EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK … #define EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK … #define EXYNOS_CIEXTEN_YUV444_OUT … /* FIMC Clock Source Select register */ #define EXYNOS_CLKSRC_HCLK … #define EXYNOS_CLKSRC_HCLK_MASK … #define EXYNOS_CLKSRC_SCLK … /* SYSREG for FIMC writeback */ #define SYSREG_CAMERA_BLK … #define SYSREG_FIMD0WB_DEST_MASK … #define SYSREG_FIMD0WB_DEST_SHIFT … #endif /* EXYNOS_REGS_FIMC_H */
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