linux/drivers/gpu/drm/rockchip/rockchip_drm_vop.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
 * Author:Mark Yao <[email protected]>
 */

#ifndef _ROCKCHIP_DRM_VOP_H
#define _ROCKCHIP_DRM_VOP_H

/*
 * major: IP major version, used for IP structure
 * minor: big feature change under same structure
 */
#define VOP_VERSION(major, minor) …
#define VOP_MAJOR(version) …
#define VOP_MINOR(version) …

#define NUM_YUV2YUV_COEFFICIENTS …

/* AFBC supports a number of configurable modes. Relevant to us is block size
 * (16x16 or 32x8), storage modifiers (SPARSE, SPLIT), and the YUV-like
 * colourspace transform (YTR). 16x16 SPARSE mode is always used. SPLIT mode
 * could be enabled via the hreg_block_split register, but is not currently
 * handled. The colourspace transform is implicitly always assumed by the
 * decoder, so consumers must use this transform as well.
 *
 * Failure to match modifiers will cause errors displaying AFBC buffers
 * produced by conformant AFBC producers, including Mesa.
 */
#define ROCKCHIP_AFBC_MOD …

enum vop_data_format { … };

struct vop_rect { … };

struct vop_reg { … };

struct vop_afbc { … };

struct vop_modeset { … };

struct vop_output { … };

struct vop_common { … };

struct vop_misc { … };

struct vop_intr { … };

struct vop_scl_extension { … };

struct vop_scl_regs { … };

struct vop_yuv2yuv_phy { … };

struct vop_win_phy { … };

struct vop_win_yuv2yuv_data { … };

struct vop_win_data { … };

struct vop_data { … };

/* interrupt define */
#define DSP_HOLD_VALID_INTR …
#define FS_INTR …
#define LINE_FLAG_INTR …
#define BUS_ERROR_INTR …

#define INTR_MASK …

#define DSP_HOLD_VALID_INTR_EN(x) …
#define FS_INTR_EN(x) …
#define LINE_FLAG_INTR_EN(x) …
#define BUS_ERROR_INTR_EN(x) …
#define DSP_HOLD_VALID_INTR_MASK …
#define FS_INTR_MASK …
#define LINE_FLAG_INTR_MASK …
#define BUS_ERROR_INTR_MASK …

#define INTR_CLR_SHIFT …
#define DSP_HOLD_VALID_INTR_CLR …
#define FS_INTR_CLR …
#define LINE_FLAG_INTR_CLR …
#define BUS_ERROR_INTR_CLR …

#define DSP_LINE_NUM(x) …
#define DSP_LINE_NUM_MASK …

/* src alpha ctrl define */
#define SRC_FADING_VALUE(x) …
#define SRC_GLOBAL_ALPHA(x) …
#define SRC_FACTOR_M0(x) …
#define SRC_ALPHA_CAL_M0(x) …
#define SRC_BLEND_M0(x) …
#define SRC_ALPHA_M0(x) …
#define SRC_COLOR_M0(x) …
#define SRC_ALPHA_EN(x) …
/* dst alpha ctrl define */
#define DST_FACTOR_M0(x) …

enum alpha_mode { … };

enum global_blend_mode { … };

enum alpha_cal_mode { … };

enum color_mode { … };

enum factor_mode { … };

enum scale_mode { … };

enum lb_mode { … };

enum sacle_up_mode { … };

enum scale_down_mode { … };

enum dither_down_mode { … };

enum dither_down_mode_sel { … };

enum vop_pol { … };

#define FRAC_16_16(mult, div) …
#define SCL_FT_DEFAULT_FIXPOINT_SHIFT …
#define SCL_MAX_VSKIPLINES …
#define MIN_SCL_FT_AFTER_VSKIP …

static inline uint16_t scl_cal_scale(int src, int dst, int shift)
{ … }

static inline uint16_t scl_cal_scale2(int src, int dst)
{ … }

#define GET_SCL_FT_BILI_DN(src, dst) …
#define GET_SCL_FT_BILI_UP(src, dst) …
#define GET_SCL_FT_BIC(src, dst) …

static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
					     int vskiplines)
{ … }

static inline enum scale_mode scl_get_scl_mode(int src, int dst)
{ … }

static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
{ … }

static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
{ … }

extern const struct component_ops vop_component_ops;
#endif /* _ROCKCHIP_DRM_VOP_H */