/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> */ #ifndef _ROCKCHIP_DRM_VOP2_H #define _ROCKCHIP_DRM_VOP2_H #include <linux/regmap.h> #include <drm/drm_modes.h> #include "rockchip_drm_vop.h" #define VOP2_VP_FEATURE_OUTPUT_10BIT … #define VOP2_FEATURE_HAS_SYS_GRF … #define VOP2_FEATURE_HAS_VO0_GRF … #define VOP2_FEATURE_HAS_VO1_GRF … #define VOP2_FEATURE_HAS_VOP_GRF … #define VOP2_FEATURE_HAS_SYS_PMU … #define WIN_FEATURE_AFBDC … #define WIN_FEATURE_CLUSTER … #define HIWORD_UPDATE(v, h, l) … /* * the delay number of a window in different mode. */ enum win_dly_mode { … }; enum vop2_scale_up_mode { … }; enum vop2_scale_down_mode { … }; /* * vop2 internal power domain id, * should be all none zero, 0 will be treat as invalid; */ #define VOP2_PD_CLUSTER0 … #define VOP2_PD_CLUSTER1 … #define VOP2_PD_CLUSTER2 … #define VOP2_PD_CLUSTER3 … #define VOP2_PD_DSC_8K … #define VOP2_PD_DSC_4K … #define VOP2_PD_ESMART … enum vop2_win_regs { … }; struct vop2_win_data { … }; struct vop2_video_port_data { … }; struct vop2_data { … }; /* interrupt define */ #define FS_NEW_INTR … #define ADDR_SAME_INTR … #define LINE_FLAG1_INTR … #define WIN0_EMPTY_INTR … #define WIN1_EMPTY_INTR … #define WIN2_EMPTY_INTR … #define WIN3_EMPTY_INTR … #define HWC_EMPTY_INTR … #define POST_BUF_EMPTY_INTR … #define PWM_GEN_INTR … #define DMA_FINISH_INTR … #define FS_FIELD_INTR … #define FE_INTR … #define WB_UV_FIFO_FULL_INTR … #define WB_YRGB_FIFO_FULL_INTR … #define WB_COMPLETE_INTR … enum vop_csc_format { … }; enum src_factor_mode { … }; enum dst_factor_mode { … }; #define RK3568_GRF_VO_CON1 … #define RK3588_GRF_SOC_CON1 … #define RK3588_GRF_VOP_CON2 … #define RK3588_GRF_VO1_CON0 … /* System registers definition */ #define RK3568_REG_CFG_DONE … #define RK3568_VERSION_INFO … #define RK3568_SYS_AUTO_GATING_CTRL … #define RK3568_SYS_AXI_LUT_CTRL … #define RK3568_DSP_IF_EN … #define RK3568_DSP_IF_CTRL … #define RK3568_DSP_IF_POL … #define RK3588_SYS_PD_CTRL … #define RK3568_WB_CTRL … #define RK3568_WB_XSCAL_FACTOR … #define RK3568_WB_YRGB_MST … #define RK3568_WB_CBR_MST … #define RK3568_OTP_WIN_EN … #define RK3568_LUT_PORT_SEL … #define RK3568_SYS_STATUS0 … #define RK3568_VP_LINE_FLAG(vp) … #define RK3568_SYS0_INT_EN … #define RK3568_SYS0_INT_CLR … #define RK3568_SYS0_INT_STATUS … #define RK3568_SYS1_INT_EN … #define RK3568_SYS1_INT_CLR … #define RK3568_SYS1_INT_STATUS … #define RK3568_VP_INT_EN(vp) … #define RK3568_VP_INT_CLR(vp) … #define RK3568_VP_INT_STATUS(vp) … #define RK3568_VP_INT_RAW_STATUS(vp) … /* Video Port registers definition */ #define RK3568_VP0_CTRL_BASE … #define RK3568_VP1_CTRL_BASE … #define RK3568_VP2_CTRL_BASE … #define RK3588_VP3_CTRL_BASE … #define RK3568_VP_DSP_CTRL … #define RK3568_VP_MIPI_CTRL … #define RK3568_VP_COLOR_BAR_CTRL … #define RK3588_VP_CLK_CTRL … #define RK3568_VP_3D_LUT_CTRL … #define RK3568_VP_3D_LUT_MST … #define RK3568_VP_DSP_BG … #define RK3568_VP_PRE_SCAN_HTIMING … #define RK3568_VP_POST_DSP_HACT_INFO … #define RK3568_VP_POST_DSP_VACT_INFO … #define RK3568_VP_POST_SCL_FACTOR_YRGB … #define RK3568_VP_POST_SCL_CTRL … #define RK3568_VP_POST_DSP_VACT_INFO_F1 … #define RK3568_VP_DSP_HTOTAL_HS_END … #define RK3568_VP_DSP_HACT_ST_END … #define RK3568_VP_DSP_VTOTAL_VS_END … #define RK3568_VP_DSP_VACT_ST_END … #define RK3568_VP_DSP_VS_ST_END_F1 … #define RK3568_VP_DSP_VACT_ST_END_F1 … #define RK3568_VP_BCSH_CTRL … #define RK3568_VP_BCSH_BCS … #define RK3568_VP_BCSH_H … #define RK3568_VP_BCSH_COLOR_BAR … /* Overlay registers definition */ #define RK3568_OVL_CTRL … #define RK3568_OVL_LAYER_SEL … #define RK3568_OVL_PORT_SEL … #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL … #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL … #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL … #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL … #define RK3568_MIX0_SRC_COLOR_CTRL … #define RK3568_MIX0_DST_COLOR_CTRL … #define RK3568_MIX0_SRC_ALPHA_CTRL … #define RK3568_MIX0_DST_ALPHA_CTRL … #define RK3568_HDR0_SRC_COLOR_CTRL … #define RK3568_HDR0_DST_COLOR_CTRL … #define RK3568_HDR0_SRC_ALPHA_CTRL … #define RK3568_HDR0_DST_ALPHA_CTRL … #define RK3568_VP_BG_MIX_CTRL(vp) … #define RK3568_CLUSTER_DLY_NUM … #define RK3568_SMART_DLY_NUM … /* Cluster register definition, offset relative to window base */ #define RK3568_CLUSTER0_CTRL_BASE … #define RK3568_CLUSTER1_CTRL_BASE … #define RK3588_CLUSTER2_CTRL_BASE … #define RK3588_CLUSTER3_CTRL_BASE … #define RK3568_ESMART0_CTRL_BASE … #define RK3568_ESMART1_CTRL_BASE … #define RK3568_SMART0_CTRL_BASE … #define RK3568_SMART1_CTRL_BASE … #define RK3588_ESMART2_CTRL_BASE … #define RK3588_ESMART3_CTRL_BASE … #define RK3568_CLUSTER_WIN_CTRL0 … #define RK3568_CLUSTER_WIN_CTRL1 … #define RK3568_CLUSTER_WIN_YRGB_MST … #define RK3568_CLUSTER_WIN_CBR_MST … #define RK3568_CLUSTER_WIN_VIR … #define RK3568_CLUSTER_WIN_ACT_INFO … #define RK3568_CLUSTER_WIN_DSP_INFO … #define RK3568_CLUSTER_WIN_DSP_ST … #define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB … #define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET … #define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL … #define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE … #define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR … #define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH … #define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE … #define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET … #define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET … #define RK3568_CLUSTER_WIN_AFBCD_CTRL … #define RK3568_CLUSTER_CTRL … /* (E)smart register definition, offset relative to window base */ #define RK3568_SMART_CTRL0 … #define RK3568_SMART_CTRL1 … #define RK3568_SMART_REGION0_CTRL … #define RK3568_SMART_REGION0_YRGB_MST … #define RK3568_SMART_REGION0_CBR_MST … #define RK3568_SMART_REGION0_VIR … #define RK3568_SMART_REGION0_ACT_INFO … #define RK3568_SMART_REGION0_DSP_INFO … #define RK3568_SMART_REGION0_DSP_ST … #define RK3568_SMART_REGION0_SCL_CTRL … #define RK3568_SMART_REGION0_SCL_FACTOR_YRGB … #define RK3568_SMART_REGION0_SCL_FACTOR_CBR … #define RK3568_SMART_REGION0_SCL_OFFSET … #define RK3568_SMART_REGION1_CTRL … #define RK3568_SMART_REGION1_YRGB_MST … #define RK3568_SMART_REGION1_CBR_MST … #define RK3568_SMART_REGION1_VIR … #define RK3568_SMART_REGION1_ACT_INFO … #define RK3568_SMART_REGION1_DSP_INFO … #define RK3568_SMART_REGION1_DSP_ST … #define RK3568_SMART_REGION1_SCL_CTRL … #define RK3568_SMART_REGION1_SCL_FACTOR_YRGB … #define RK3568_SMART_REGION1_SCL_FACTOR_CBR … #define RK3568_SMART_REGION1_SCL_OFFSET … #define RK3568_SMART_REGION2_CTRL … #define RK3568_SMART_REGION2_YRGB_MST … #define RK3568_SMART_REGION2_CBR_MST … #define RK3568_SMART_REGION2_VIR … #define RK3568_SMART_REGION2_ACT_INFO … #define RK3568_SMART_REGION2_DSP_INFO … #define RK3568_SMART_REGION2_DSP_ST … #define RK3568_SMART_REGION2_SCL_CTRL … #define RK3568_SMART_REGION2_SCL_FACTOR_YRGB … #define RK3568_SMART_REGION2_SCL_FACTOR_CBR … #define RK3568_SMART_REGION2_SCL_OFFSET … #define RK3568_SMART_REGION3_CTRL … #define RK3568_SMART_REGION3_YRGB_MST … #define RK3568_SMART_REGION3_CBR_MST … #define RK3568_SMART_REGION3_VIR … #define RK3568_SMART_REGION3_ACT_INFO … #define RK3568_SMART_REGION3_DSP_INFO … #define RK3568_SMART_REGION3_DSP_ST … #define RK3568_SMART_REGION3_SCL_CTRL … #define RK3568_SMART_REGION3_SCL_FACTOR_YRGB … #define RK3568_SMART_REGION3_SCL_FACTOR_CBR … #define RK3568_SMART_REGION3_SCL_OFFSET … #define RK3568_SMART_COLOR_KEY_CTRL … /* HDR register definition */ #define RK3568_HDR_LUT_CTRL … #define RK3568_HDR_LUT_MST … #define RK3568_SDR2HDR_CTRL … #define RK3568_HDR2SDR_CTRL … #define RK3568_HDR2SDR_SRC_RANGE … #define RK3568_HDR2SDR_NORMFACEETF … #define RK3568_HDR2SDR_DST_RANGE … #define RK3568_HDR2SDR_NORMFACCGAMMA … #define RK3568_HDR_EETF_OETF_Y0 … #define RK3568_HDR_SAT_Y0 … #define RK3568_HDR_EOTF_OETF_Y0 … #define RK3568_HDR_OETF_DX_POW1 … #define RK3568_HDR_OETF_XN1 … #define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN … #define RK3568_VP_DSP_CTRL__STANDBY … #define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE … #define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL … #define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN … #define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN … #define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y … #define RK3568_VP_DSP_CTRL__DSP_RG_SWAP … #define RK3568_VP_DSP_CTRL__DSP_RB_SWAP … #define RK3568_VP_DSP_CTRL__DSP_BG_SWAP … #define RK3568_VP_DSP_CTRL__DSP_INTERLACE … #define RK3568_VP_DSP_CTRL__DSP_FILED_POL … #define RK3568_VP_DSP_CTRL__P2I_EN … #define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV … #define RK3568_VP_DSP_CTRL__OUT_MODE … #define RK3588_VP_CLK_CTRL__DCLK_OUT_DIV … #define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV … #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN … #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN … #define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX … #define RK3568_SYS_DSP_INFACE_EN_LVDS1 … #define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX … #define RK3568_SYS_DSP_INFACE_EN_MIPI1 … #define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX … #define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX … #define RK3568_SYS_DSP_INFACE_EN_EDP_MUX … #define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX … #define RK3568_SYS_DSP_INFACE_EN_RGB_MUX … #define RK3568_SYS_DSP_INFACE_EN_LVDS0 … #define RK3568_SYS_DSP_INFACE_EN_MIPI0 … #define RK3568_SYS_DSP_INFACE_EN_EDP … #define RK3568_SYS_DSP_INFACE_EN_HDMI … #define RK3568_SYS_DSP_INFACE_EN_RGB … #define RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX … #define RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX … #define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX … #define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX … #define RK3588_SYS_DSP_INFACE_EN_DP1_MUX … #define RK3588_SYS_DSP_INFACE_EN_DP0_MUX … #define RK3588_SYS_DSP_INFACE_EN_DPI … #define RK3588_SYS_DSP_INFACE_EN_MIPI1 … #define RK3588_SYS_DSP_INFACE_EN_MIPI0 … #define RK3588_SYS_DSP_INFACE_EN_HDMI1 … #define RK3588_SYS_DSP_INFACE_EN_EDP1 … #define RK3588_SYS_DSP_INFACE_EN_HDMI0 … #define RK3588_SYS_DSP_INFACE_EN_EDP0 … #define RK3588_SYS_DSP_INFACE_EN_DP1 … #define RK3588_SYS_DSP_INFACE_EN_DP0 … #define RK3588_DSP_IF_MIPI1_PCLK_DIV … #define RK3588_DSP_IF_MIPI0_PCLK_DIV … #define RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV … #define RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV … #define RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV … #define RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV … #define RK3568_DSP_IF_POL__MIPI_PIN_POL … #define RK3568_DSP_IF_POL__EDP_PIN_POL … #define RK3568_DSP_IF_POL__HDMI_PIN_POL … #define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL … #define RK3588_DSP_IF_POL__DP1_PIN_POL … #define RK3588_DSP_IF_POL__DP0_PIN_POL … #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK … #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 … #define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN … #define RK3568_DSP_IF_POL__CFG_DONE_IMD … #define VOP2_SYS_AXI_BUS_NUM … #define VOP2_CLUSTER_YUV444_10 … #define VOP2_COLOR_KEY_MASK … #define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD … #define RK3568_OVL_CTRL__YUV_MODE(vp) … #define RK3568_VP_BG_MIX_CTRL__BG_DLY … #define RK3568_OVL_PORT_SEL__SEL_PORT … #define RK3568_OVL_PORT_SEL__SMART1 … #define RK3568_OVL_PORT_SEL__SMART0 … #define RK3588_OVL_PORT_SEL__ESMART3 … #define RK3588_OVL_PORT_SEL__ESMART2 … #define RK3568_OVL_PORT_SEL__ESMART1 … #define RK3568_OVL_PORT_SEL__ESMART0 … #define RK3588_OVL_PORT_SEL__CLUSTER3 … #define RK3588_OVL_PORT_SEL__CLUSTER2 … #define RK3568_OVL_PORT_SEL__CLUSTER1 … #define RK3568_OVL_PORT_SEL__CLUSTER0 … #define RK3568_OVL_PORT_SET__PORT2_MUX … #define RK3568_OVL_PORT_SET__PORT1_MUX … #define RK3568_OVL_PORT_SET__PORT0_MUX … #define RK3568_OVL_LAYER_SEL__LAYER(layer, x) … #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1 … #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0 … #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1 … #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 … #define RK3568_CLUSTER_WIN_CTRL0__WIN0_EN … #define RK3568_SMART_REGION0_CTRL__WIN0_EN … #define RK3568_SMART_DLY_NUM__SMART1 … #define RK3568_SMART_DLY_NUM__SMART0 … #define RK3568_SMART_DLY_NUM__ESMART1 … #define RK3568_SMART_DLY_NUM__ESMART0 … #define VP_INT_DSP_HOLD_VALID … #define VP_INT_FS_FIELD … #define VP_INT_POST_BUF_EMPTY … #define VP_INT_LINE_FLAG1 … #define VP_INT_LINE_FLAG0 … #define VOP2_INT_BUS_ERRPR … #define VP_INT_FS … #define POLFLAG_DCLK_INV … enum vop2_layer_phy_id { … }; extern const struct component_ops vop2_component_ops; #endif /* _ROCKCHIP_DRM_VOP2_H */
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