/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <[email protected]> */ #ifndef _ROCKCHIP_VOP_REG_H #define _ROCKCHIP_VOP_REG_H /* rk3288 register definition */ #define RK3288_REG_CFG_DONE … #define RK3288_VERSION_INFO … #define RK3288_SYS_CTRL … #define RK3288_SYS_CTRL1 … #define RK3288_DSP_CTRL0 … #define RK3288_DSP_CTRL1 … #define RK3288_DSP_BG … #define RK3288_MCU_CTRL … #define RK3288_INTR_CTRL0 … #define RK3288_INTR_CTRL1 … #define RK3288_WIN0_CTRL0 … #define RK3288_WIN0_CTRL1 … #define RK3288_WIN0_COLOR_KEY … #define RK3288_WIN0_VIR … #define RK3288_WIN0_YRGB_MST … #define RK3288_WIN0_CBR_MST … #define RK3288_WIN0_ACT_INFO … #define RK3288_WIN0_DSP_INFO … #define RK3288_WIN0_DSP_ST … #define RK3288_WIN0_SCL_FACTOR_YRGB … #define RK3288_WIN0_SCL_FACTOR_CBR … #define RK3288_WIN0_SCL_OFFSET … #define RK3288_WIN0_SRC_ALPHA_CTRL … #define RK3288_WIN0_DST_ALPHA_CTRL … #define RK3288_WIN0_FADING_CTRL … #define RK3288_WIN0_CTRL2 … /* win1 register */ #define RK3288_WIN1_CTRL0 … #define RK3288_WIN1_CTRL1 … #define RK3288_WIN1_COLOR_KEY … #define RK3288_WIN1_VIR … #define RK3288_WIN1_YRGB_MST … #define RK3288_WIN1_CBR_MST … #define RK3288_WIN1_ACT_INFO … #define RK3288_WIN1_DSP_INFO … #define RK3288_WIN1_DSP_ST … #define RK3288_WIN1_SCL_FACTOR_YRGB … #define RK3288_WIN1_SCL_FACTOR_CBR … #define RK3288_WIN1_SCL_OFFSET … #define RK3288_WIN1_SRC_ALPHA_CTRL … #define RK3288_WIN1_DST_ALPHA_CTRL … #define RK3288_WIN1_FADING_CTRL … /* win2 register */ #define RK3288_WIN2_CTRL0 … #define RK3288_WIN2_CTRL1 … #define RK3288_WIN2_VIR0_1 … #define RK3288_WIN2_VIR2_3 … #define RK3288_WIN2_MST0 … #define RK3288_WIN2_DSP_INFO0 … #define RK3288_WIN2_DSP_ST0 … #define RK3288_WIN2_COLOR_KEY … #define RK3288_WIN2_MST1 … #define RK3288_WIN2_DSP_INFO1 … #define RK3288_WIN2_DSP_ST1 … #define RK3288_WIN2_SRC_ALPHA_CTRL … #define RK3288_WIN2_MST2 … #define RK3288_WIN2_DSP_INFO2 … #define RK3288_WIN2_DSP_ST2 … #define RK3288_WIN2_DST_ALPHA_CTRL … #define RK3288_WIN2_MST3 … #define RK3288_WIN2_DSP_INFO3 … #define RK3288_WIN2_DSP_ST3 … #define RK3288_WIN2_FADING_CTRL … /* win3 register */ #define RK3288_WIN3_CTRL0 … #define RK3288_WIN3_CTRL1 … #define RK3288_WIN3_VIR0_1 … #define RK3288_WIN3_VIR2_3 … #define RK3288_WIN3_MST0 … #define RK3288_WIN3_DSP_INFO0 … #define RK3288_WIN3_DSP_ST0 … #define RK3288_WIN3_COLOR_KEY … #define RK3288_WIN3_MST1 … #define RK3288_WIN3_DSP_INFO1 … #define RK3288_WIN3_DSP_ST1 … #define RK3288_WIN3_SRC_ALPHA_CTRL … #define RK3288_WIN3_MST2 … #define RK3288_WIN3_DSP_INFO2 … #define RK3288_WIN3_DSP_ST2 … #define RK3288_WIN3_DST_ALPHA_CTRL … #define RK3288_WIN3_MST3 … #define RK3288_WIN3_DSP_INFO3 … #define RK3288_WIN3_DSP_ST3 … #define RK3288_WIN3_FADING_CTRL … /* hwc register */ #define RK3288_HWC_CTRL0 … #define RK3288_HWC_CTRL1 … #define RK3288_HWC_MST … #define RK3288_HWC_DSP_ST … #define RK3288_HWC_SRC_ALPHA_CTRL … #define RK3288_HWC_DST_ALPHA_CTRL … #define RK3288_HWC_FADING_CTRL … /* post process register */ #define RK3288_POST_DSP_HACT_INFO … #define RK3288_POST_DSP_VACT_INFO … #define RK3288_POST_SCL_FACTOR_YRGB … #define RK3288_POST_SCL_CTRL … #define RK3288_POST_DSP_VACT_INFO_F1 … #define RK3288_DSP_HTOTAL_HS_END … #define RK3288_DSP_HACT_ST_END … #define RK3288_DSP_VTOTAL_VS_END … #define RK3288_DSP_VACT_ST_END … #define RK3288_DSP_VS_ST_END_F1 … #define RK3288_DSP_VACT_ST_END_F1 … /* register definition end */ /* rk3368 register definition */ #define RK3368_REG_CFG_DONE … #define RK3368_VERSION_INFO … #define RK3368_SYS_CTRL … #define RK3368_SYS_CTRL1 … #define RK3368_DSP_CTRL0 … #define RK3368_DSP_CTRL1 … #define RK3368_DSP_BG … #define RK3368_MCU_CTRL … #define RK3368_LINE_FLAG … #define RK3368_INTR_EN … #define RK3368_INTR_CLEAR … #define RK3368_INTR_STATUS … #define RK3368_WIN0_CTRL0 … #define RK3368_WIN0_CTRL1 … #define RK3368_WIN0_COLOR_KEY … #define RK3368_WIN0_VIR … #define RK3368_WIN0_YRGB_MST … #define RK3368_WIN0_CBR_MST … #define RK3368_WIN0_ACT_INFO … #define RK3368_WIN0_DSP_INFO … #define RK3368_WIN0_DSP_ST … #define RK3368_WIN0_SCL_FACTOR_YRGB … #define RK3368_WIN0_SCL_FACTOR_CBR … #define RK3368_WIN0_SCL_OFFSET … #define RK3368_WIN0_SRC_ALPHA_CTRL … #define RK3368_WIN0_DST_ALPHA_CTRL … #define RK3368_WIN0_FADING_CTRL … #define RK3368_WIN0_CTRL2 … #define RK3368_WIN1_CTRL0 … #define RK3368_WIN1_CTRL1 … #define RK3368_WIN1_COLOR_KEY … #define RK3368_WIN1_VIR … #define RK3368_WIN1_YRGB_MST … #define RK3368_WIN1_CBR_MST … #define RK3368_WIN1_ACT_INFO … #define RK3368_WIN1_DSP_INFO … #define RK3368_WIN1_DSP_ST … #define RK3368_WIN1_SCL_FACTOR_YRGB … #define RK3368_WIN1_SCL_FACTOR_CBR … #define RK3368_WIN1_SCL_OFFSET … #define RK3368_WIN1_SRC_ALPHA_CTRL … #define RK3368_WIN1_DST_ALPHA_CTRL … #define RK3368_WIN1_FADING_CTRL … #define RK3368_WIN1_CTRL2 … #define RK3368_WIN2_CTRL0 … #define RK3368_WIN2_CTRL1 … #define RK3368_WIN2_VIR0_1 … #define RK3368_WIN2_VIR2_3 … #define RK3368_WIN2_MST0 … #define RK3368_WIN2_DSP_INFO0 … #define RK3368_WIN2_DSP_ST0 … #define RK3368_WIN2_COLOR_KEY … #define RK3368_WIN2_MST1 … #define RK3368_WIN2_DSP_INFO1 … #define RK3368_WIN2_DSP_ST1 … #define RK3368_WIN2_SRC_ALPHA_CTRL … #define RK3368_WIN2_MST2 … #define RK3368_WIN2_DSP_INFO2 … #define RK3368_WIN2_DSP_ST2 … #define RK3368_WIN2_DST_ALPHA_CTRL … #define RK3368_WIN2_MST3 … #define RK3368_WIN2_DSP_INFO3 … #define RK3368_WIN2_DSP_ST3 … #define RK3368_WIN2_FADING_CTRL … #define RK3368_WIN3_CTRL0 … #define RK3368_WIN3_CTRL1 … #define RK3368_WIN3_VIR0_1 … #define RK3368_WIN3_VIR2_3 … #define RK3368_WIN3_MST0 … #define RK3368_WIN3_DSP_INFO0 … #define RK3368_WIN3_DSP_ST0 … #define RK3368_WIN3_COLOR_KEY … #define RK3368_WIN3_MST1 … #define RK3368_WIN3_DSP_INFO1 … #define RK3368_WIN3_DSP_ST1 … #define RK3368_WIN3_SRC_ALPHA_CTRL … #define RK3368_WIN3_MST2 … #define RK3368_WIN3_DSP_INFO2 … #define RK3368_WIN3_DSP_ST2 … #define RK3368_WIN3_DST_ALPHA_CTRL … #define RK3368_WIN3_MST3 … #define RK3368_WIN3_DSP_INFO3 … #define RK3368_WIN3_DSP_ST3 … #define RK3368_WIN3_FADING_CTRL … #define RK3368_HWC_CTRL0 … #define RK3368_HWC_CTRL1 … #define RK3368_HWC_MST … #define RK3368_HWC_DSP_ST … #define RK3368_HWC_SRC_ALPHA_CTRL … #define RK3368_HWC_DST_ALPHA_CTRL … #define RK3368_HWC_FADING_CTRL … #define RK3368_HWC_RESERVED1 … #define RK3368_POST_DSP_HACT_INFO … #define RK3368_POST_DSP_VACT_INFO … #define RK3368_POST_SCL_FACTOR_YRGB … #define RK3368_POST_RESERVED … #define RK3368_POST_SCL_CTRL … #define RK3368_POST_DSP_VACT_INFO_F1 … #define RK3368_DSP_HTOTAL_HS_END … #define RK3368_DSP_HACT_ST_END … #define RK3368_DSP_VTOTAL_VS_END … #define RK3368_DSP_VACT_ST_END … #define RK3368_DSP_VS_ST_END_F1 … #define RK3368_DSP_VACT_ST_END_F1 … #define RK3368_PWM_CTRL … #define RK3368_PWM_PERIOD_HPR … #define RK3368_PWM_DUTY_LPR … #define RK3368_PWM_CNT … #define RK3368_BCSH_COLOR_BAR … #define RK3368_BCSH_BCS … #define RK3368_BCSH_H … #define RK3368_BCSH_CTRL … #define RK3368_CABC_CTRL0 … #define RK3368_CABC_CTRL1 … #define RK3368_CABC_CTRL2 … #define RK3368_CABC_CTRL3 … #define RK3368_CABC_GAUSS_LINE0_0 … #define RK3368_CABC_GAUSS_LINE0_1 … #define RK3368_CABC_GAUSS_LINE1_0 … #define RK3368_CABC_GAUSS_LINE1_1 … #define RK3368_CABC_GAUSS_LINE2_0 … #define RK3368_CABC_GAUSS_LINE2_1 … #define RK3368_FRC_LOWER01_0 … #define RK3368_FRC_LOWER01_1 … #define RK3368_FRC_LOWER10_0 … #define RK3368_FRC_LOWER10_1 … #define RK3368_FRC_LOWER11_0 … #define RK3368_FRC_LOWER11_1 … #define RK3368_IFBDC_CTRL … #define RK3368_IFBDC_TILES_NUM … #define RK3368_IFBDC_FRAME_RST_CYCLE … #define RK3368_IFBDC_BASE_ADDR … #define RK3368_IFBDC_MB_SIZE … #define RK3368_IFBDC_CMP_INDEX_INIT … #define RK3368_IFBDC_VIR … #define RK3368_IFBDC_DEBUG0 … #define RK3368_IFBDC_DEBUG1 … #define RK3368_LATENCY_CTRL0 … #define RK3368_RD_MAX_LATENCY_NUM0 … #define RK3368_RD_LATENCY_THR_NUM0 … #define RK3368_RD_LATENCY_SAMP_NUM0 … #define RK3368_WIN0_DSP_BG … #define RK3368_WIN1_DSP_BG … #define RK3368_WIN2_DSP_BG … #define RK3368_WIN3_DSP_BG … #define RK3368_SCAN_LINE_NUM … #define RK3368_CABC_DEBUG0 … #define RK3368_CABC_DEBUG1 … #define RK3368_CABC_DEBUG2 … #define RK3368_DBG_REG_000 … #define RK3368_DBG_REG_001 … #define RK3368_DBG_REG_002 … #define RK3368_DBG_REG_003 … #define RK3368_DBG_REG_004 … #define RK3368_DBG_REG_005 … #define RK3368_DBG_REG_006 … #define RK3368_DBG_REG_007 … #define RK3368_DBG_REG_008 … #define RK3368_DBG_REG_016 … #define RK3368_DBG_REG_017 … #define RK3368_DBG_REG_018 … #define RK3368_DBG_REG_019 … #define RK3368_DBG_REG_020 … #define RK3368_DBG_REG_021 … #define RK3368_DBG_REG_022 … #define RK3368_DBG_REG_023 … #define RK3368_DBG_REG_028 … #define RK3368_MMU_DTE_ADDR … #define RK3368_MMU_STATUS … #define RK3368_MMU_COMMAND … #define RK3368_MMU_PAGE_FAULT_ADDR … #define RK3368_MMU_ZAP_ONE_LINE … #define RK3368_MMU_INT_RAWSTAT … #define RK3368_MMU_INT_CLEAR … #define RK3368_MMU_INT_MASK … #define RK3368_MMU_INT_STATUS … #define RK3368_MMU_AUTO_GATING … #define RK3368_WIN2_LUT_ADDR … #define RK3368_WIN3_LUT_ADDR … #define RK3368_HWC_LUT_ADDR … #define RK3368_GAMMA_LUT_ADDR … #define RK3368_CABC_GAMMA_LUT_ADDR … #define RK3368_MCU_BYPASS_WPORT … #define RK3368_MCU_BYPASS_RPORT … /* rk3368 register definition end */ #define RK3366_REG_CFG_DONE … #define RK3366_VERSION_INFO … #define RK3366_SYS_CTRL … #define RK3366_SYS_CTRL1 … #define RK3366_DSP_CTRL0 … #define RK3366_DSP_CTRL1 … #define RK3366_DSP_BG … #define RK3366_MCU_CTRL … #define RK3366_WB_CTRL0 … #define RK3366_WB_CTRL1 … #define RK3366_WB_YRGB_MST … #define RK3366_WB_CBR_MST … #define RK3366_WIN0_CTRL0 … #define RK3366_WIN0_CTRL1 … #define RK3366_WIN0_COLOR_KEY … #define RK3366_WIN0_VIR … #define RK3366_WIN0_YRGB_MST … #define RK3366_WIN0_CBR_MST … #define RK3366_WIN0_ACT_INFO … #define RK3366_WIN0_DSP_INFO … #define RK3366_WIN0_DSP_ST … #define RK3366_WIN0_SCL_FACTOR_YRGB … #define RK3366_WIN0_SCL_FACTOR_CBR … #define RK3366_WIN0_SCL_OFFSET … #define RK3366_WIN0_SRC_ALPHA_CTRL … #define RK3366_WIN0_DST_ALPHA_CTRL … #define RK3366_WIN0_FADING_CTRL … #define RK3366_WIN0_CTRL2 … #define RK3366_WIN1_CTRL0 … #define RK3366_WIN1_CTRL1 … #define RK3366_WIN1_COLOR_KEY … #define RK3366_WIN1_VIR … #define RK3366_WIN1_YRGB_MST … #define RK3366_WIN1_CBR_MST … #define RK3366_WIN1_ACT_INFO … #define RK3366_WIN1_DSP_INFO … #define RK3366_WIN1_DSP_ST … #define RK3366_WIN1_SCL_FACTOR_YRGB … #define RK3366_WIN1_SCL_FACTOR_CBR … #define RK3366_WIN1_SCL_OFFSET … #define RK3366_WIN1_SRC_ALPHA_CTRL … #define RK3366_WIN1_DST_ALPHA_CTRL … #define RK3366_WIN1_FADING_CTRL … #define RK3366_WIN1_CTRL2 … #define RK3366_WIN2_CTRL0 … #define RK3366_WIN2_CTRL1 … #define RK3366_WIN2_VIR0_1 … #define RK3366_WIN2_VIR2_3 … #define RK3366_WIN2_MST0 … #define RK3366_WIN2_DSP_INFO0 … #define RK3366_WIN2_DSP_ST0 … #define RK3366_WIN2_COLOR_KEY … #define RK3366_WIN2_MST1 … #define RK3366_WIN2_DSP_INFO1 … #define RK3366_WIN2_DSP_ST1 … #define RK3366_WIN2_SRC_ALPHA_CTRL … #define RK3366_WIN2_MST2 … #define RK3366_WIN2_DSP_INFO2 … #define RK3366_WIN2_DSP_ST2 … #define RK3366_WIN2_DST_ALPHA_CTRL … #define RK3366_WIN2_MST3 … #define RK3366_WIN2_DSP_INFO3 … #define RK3366_WIN2_DSP_ST3 … #define RK3366_WIN2_FADING_CTRL … #define RK3366_WIN3_CTRL0 … #define RK3366_WIN3_CTRL1 … #define RK3366_WIN3_VIR0_1 … #define RK3366_WIN3_VIR2_3 … #define RK3366_WIN3_MST0 … #define RK3366_WIN3_DSP_INFO0 … #define RK3366_WIN3_DSP_ST0 … #define RK3366_WIN3_COLOR_KEY … #define RK3366_WIN3_MST1 … #define RK3366_WIN3_DSP_INFO1 … #define RK3366_WIN3_DSP_ST1 … #define RK3366_WIN3_SRC_ALPHA_CTRL … #define RK3366_WIN3_MST2 … #define RK3366_WIN3_DSP_INFO2 … #define RK3366_WIN3_DSP_ST2 … #define RK3366_WIN3_DST_ALPHA_CTRL … #define RK3366_WIN3_MST3 … #define RK3366_WIN3_DSP_INFO3 … #define RK3366_WIN3_DSP_ST3 … #define RK3366_WIN3_FADING_CTRL … #define RK3366_HWC_CTRL0 … #define RK3366_HWC_CTRL1 … #define RK3366_HWC_MST … #define RK3366_HWC_DSP_ST … #define RK3366_HWC_SRC_ALPHA_CTRL … #define RK3366_HWC_DST_ALPHA_CTRL … #define RK3366_HWC_FADING_CTRL … #define RK3366_HWC_RESERVED1 … #define RK3366_POST_DSP_HACT_INFO … #define RK3366_POST_DSP_VACT_INFO … #define RK3366_POST_SCL_FACTOR_YRGB … #define RK3366_POST_RESERVED … #define RK3366_POST_SCL_CTRL … #define RK3366_POST_DSP_VACT_INFO_F1 … #define RK3366_DSP_HTOTAL_HS_END … #define RK3366_DSP_HACT_ST_END … #define RK3366_DSP_VTOTAL_VS_END … #define RK3366_DSP_VACT_ST_END … #define RK3366_DSP_VS_ST_END_F1 … #define RK3366_DSP_VACT_ST_END_F1 … #define RK3366_PWM_CTRL … #define RK3366_PWM_PERIOD_HPR … #define RK3366_PWM_DUTY_LPR … #define RK3366_PWM_CNT … #define RK3366_BCSH_COLOR_BAR … #define RK3366_BCSH_BCS … #define RK3366_BCSH_H … #define RK3366_BCSH_CTRL … #define RK3366_CABC_CTRL0 … #define RK3366_CABC_CTRL1 … #define RK3366_CABC_CTRL2 … #define RK3366_CABC_CTRL3 … #define RK3366_CABC_GAUSS_LINE0_0 … #define RK3366_CABC_GAUSS_LINE0_1 … #define RK3366_CABC_GAUSS_LINE1_0 … #define RK3366_CABC_GAUSS_LINE1_1 … #define RK3366_CABC_GAUSS_LINE2_0 … #define RK3366_CABC_GAUSS_LINE2_1 … #define RK3366_FRC_LOWER01_0 … #define RK3366_FRC_LOWER01_1 … #define RK3366_FRC_LOWER10_0 … #define RK3366_FRC_LOWER10_1 … #define RK3366_FRC_LOWER11_0 … #define RK3366_FRC_LOWER11_1 … #define RK3366_INTR_EN0 … #define RK3366_INTR_CLEAR0 … #define RK3366_INTR_STATUS0 … #define RK3366_INTR_RAW_STATUS0 … #define RK3366_INTR_EN1 … #define RK3366_INTR_CLEAR1 … #define RK3366_INTR_STATUS1 … #define RK3366_INTR_RAW_STATUS1 … #define RK3366_LINE_FLAG … #define RK3366_VOP_STATUS … #define RK3366_BLANKING_VALUE … #define RK3366_WIN0_DSP_BG … #define RK3366_WIN1_DSP_BG … #define RK3366_WIN2_DSP_BG … #define RK3366_WIN3_DSP_BG … #define RK3366_WIN2_LUT_ADDR … #define RK3366_WIN3_LUT_ADDR … #define RK3366_HWC_LUT_ADDR … #define RK3366_GAMMA0_LUT_ADDR … #define RK3366_GAMMA1_LUT_ADDR … #define RK3366_CABC_GAMMA_LUT_ADDR … #define RK3366_MCU_BYPASS_WPORT … #define RK3366_MCU_BYPASS_RPORT … #define RK3366_MMU_DTE_ADDR … #define RK3366_MMU_STATUS … #define RK3366_MMU_COMMAND … #define RK3366_MMU_PAGE_FAULT_ADDR … #define RK3366_MMU_ZAP_ONE_LINE … #define RK3366_MMU_INT_RAWSTAT … #define RK3366_MMU_INT_CLEAR … #define RK3366_MMU_INT_MASK … #define RK3366_MMU_INT_STATUS … #define RK3366_MMU_AUTO_GATING … /* rk3399 register definition */ #define RK3399_REG_CFG_DONE … #define RK3399_VERSION_INFO … #define RK3399_SYS_CTRL … #define RK3399_SYS_CTRL1 … #define RK3399_DSP_CTRL0 … #define RK3399_DSP_CTRL1 … #define RK3399_DSP_BG … #define RK3399_MCU_CTRL … #define RK3399_WB_CTRL0 … #define RK3399_WB_CTRL1 … #define RK3399_WB_YRGB_MST … #define RK3399_WB_CBR_MST … #define RK3399_WIN0_CTRL0 … #define RK3399_WIN0_CTRL1 … #define RK3399_WIN0_COLOR_KEY … #define RK3399_WIN0_VIR … #define RK3399_WIN0_YRGB_MST … #define RK3399_WIN0_CBR_MST … #define RK3399_WIN0_ACT_INFO … #define RK3399_WIN0_DSP_INFO … #define RK3399_WIN0_DSP_ST … #define RK3399_WIN0_SCL_FACTOR_YRGB … #define RK3399_WIN0_SCL_FACTOR_CBR … #define RK3399_WIN0_SCL_OFFSET … #define RK3399_WIN0_SRC_ALPHA_CTRL … #define RK3399_WIN0_DST_ALPHA_CTRL … #define RK3399_WIN0_FADING_CTRL … #define RK3399_WIN0_CTRL2 … #define RK3399_WIN1_CTRL0 … #define RK3399_WIN1_CTRL1 … #define RK3399_WIN1_COLOR_KEY … #define RK3399_WIN1_VIR … #define RK3399_WIN1_YRGB_MST … #define RK3399_WIN1_CBR_MST … #define RK3399_WIN1_ACT_INFO … #define RK3399_WIN1_DSP_INFO … #define RK3399_WIN1_DSP_ST … #define RK3399_WIN1_SCL_FACTOR_YRGB … #define RK3399_WIN1_SCL_FACTOR_CBR … #define RK3399_WIN1_SCL_OFFSET … #define RK3399_WIN1_SRC_ALPHA_CTRL … #define RK3399_WIN1_DST_ALPHA_CTRL … #define RK3399_WIN1_FADING_CTRL … #define RK3399_WIN1_CTRL2 … #define RK3399_WIN2_CTRL0 … #define RK3399_WIN2_CTRL1 … #define RK3399_WIN2_VIR0_1 … #define RK3399_WIN2_VIR2_3 … #define RK3399_WIN2_MST0 … #define RK3399_WIN2_DSP_INFO0 … #define RK3399_WIN2_DSP_ST0 … #define RK3399_WIN2_COLOR_KEY … #define RK3399_WIN2_MST1 … #define RK3399_WIN2_DSP_INFO1 … #define RK3399_WIN2_DSP_ST1 … #define RK3399_WIN2_SRC_ALPHA_CTRL … #define RK3399_WIN2_MST2 … #define RK3399_WIN2_DSP_INFO2 … #define RK3399_WIN2_DSP_ST2 … #define RK3399_WIN2_DST_ALPHA_CTRL … #define RK3399_WIN2_MST3 … #define RK3399_WIN2_DSP_INFO3 … #define RK3399_WIN2_DSP_ST3 … #define RK3399_WIN2_FADING_CTRL … #define RK3399_WIN3_CTRL0 … #define RK3399_WIN3_CTRL1 … #define RK3399_WIN3_VIR0_1 … #define RK3399_WIN3_VIR2_3 … #define RK3399_WIN3_MST0 … #define RK3399_WIN3_DSP_INFO0 … #define RK3399_WIN3_DSP_ST0 … #define RK3399_WIN3_COLOR_KEY … #define RK3399_WIN3_MST1 … #define RK3399_WIN3_DSP_INFO1 … #define RK3399_WIN3_DSP_ST1 … #define RK3399_WIN3_SRC_ALPHA_CTRL … #define RK3399_WIN3_MST2 … #define RK3399_WIN3_DSP_INFO2 … #define RK3399_WIN3_DSP_ST2 … #define RK3399_WIN3_DST_ALPHA_CTRL … #define RK3399_WIN3_MST3 … #define RK3399_WIN3_DSP_INFO3 … #define RK3399_WIN3_DSP_ST3 … #define RK3399_WIN3_FADING_CTRL … #define RK3399_HWC_CTRL0 … #define RK3399_HWC_CTRL1 … #define RK3399_HWC_MST … #define RK3399_HWC_DSP_ST … #define RK3399_HWC_SRC_ALPHA_CTRL … #define RK3399_HWC_DST_ALPHA_CTRL … #define RK3399_HWC_FADING_CTRL … #define RK3399_HWC_RESERVED1 … #define RK3399_POST_DSP_HACT_INFO … #define RK3399_POST_DSP_VACT_INFO … #define RK3399_POST_SCL_FACTOR_YRGB … #define RK3399_POST_RESERVED … #define RK3399_POST_SCL_CTRL … #define RK3399_POST_DSP_VACT_INFO_F1 … #define RK3399_DSP_HTOTAL_HS_END … #define RK3399_DSP_HACT_ST_END … #define RK3399_DSP_VTOTAL_VS_END … #define RK3399_DSP_VACT_ST_END … #define RK3399_DSP_VS_ST_END_F1 … #define RK3399_DSP_VACT_ST_END_F1 … #define RK3399_PWM_CTRL … #define RK3399_PWM_PERIOD_HPR … #define RK3399_PWM_DUTY_LPR … #define RK3399_PWM_CNT … #define RK3399_BCSH_COLOR_BAR … #define RK3399_BCSH_BCS … #define RK3399_BCSH_H … #define RK3399_BCSH_CTRL … #define RK3399_CABC_CTRL0 … #define RK3399_CABC_CTRL1 … #define RK3399_CABC_CTRL2 … #define RK3399_CABC_CTRL3 … #define RK3399_CABC_GAUSS_LINE0_0 … #define RK3399_CABC_GAUSS_LINE0_1 … #define RK3399_CABC_GAUSS_LINE1_0 … #define RK3399_CABC_GAUSS_LINE1_1 … #define RK3399_CABC_GAUSS_LINE2_0 … #define RK3399_CABC_GAUSS_LINE2_1 … #define RK3399_FRC_LOWER01_0 … #define RK3399_FRC_LOWER01_1 … #define RK3399_FRC_LOWER10_0 … #define RK3399_FRC_LOWER10_1 … #define RK3399_FRC_LOWER11_0 … #define RK3399_FRC_LOWER11_1 … #define RK3399_AFBCD0_CTRL … #define RK3399_AFBCD0_HDR_PTR … #define RK3399_AFBCD0_PIC_SIZE … #define RK3399_AFBCD0_STATUS … #define RK3399_AFBCD1_CTRL … #define RK3399_AFBCD1_HDR_PTR … #define RK3399_AFBCD1_PIC_SIZE … #define RK3399_AFBCD1_STATUS … #define RK3399_AFBCD2_CTRL … #define RK3399_AFBCD2_HDR_PTR … #define RK3399_AFBCD2_PIC_SIZE … #define RK3399_AFBCD2_STATUS … #define RK3399_AFBCD3_CTRL … #define RK3399_AFBCD3_HDR_PTR … #define RK3399_AFBCD3_PIC_SIZE … #define RK3399_AFBCD3_STATUS … #define RK3399_INTR_EN0 … #define RK3399_INTR_CLEAR0 … #define RK3399_INTR_STATUS0 … #define RK3399_INTR_RAW_STATUS0 … #define RK3399_INTR_EN1 … #define RK3399_INTR_CLEAR1 … #define RK3399_INTR_STATUS1 … #define RK3399_INTR_RAW_STATUS1 … #define RK3399_LINE_FLAG … #define RK3399_VOP_STATUS … #define RK3399_BLANKING_VALUE … #define RK3399_MCU_BYPASS_PORT … #define RK3399_WIN0_DSP_BG … #define RK3399_WIN1_DSP_BG … #define RK3399_WIN2_DSP_BG … #define RK3399_WIN3_DSP_BG … #define RK3399_YUV2YUV_WIN … #define RK3399_YUV2YUV_POST … #define RK3399_AUTO_GATING_EN … #define RK3399_DBG_POST_REG1 … #define RK3399_WIN0_CSC_COE … #define RK3399_WIN1_CSC_COE … #define RK3399_WIN2_CSC_COE … #define RK3399_WIN3_CSC_COE … #define RK3399_HWC_CSC_COE … #define RK3399_BCSH_R2Y_CSC_COE … #define RK3399_BCSH_Y2R_CSC_COE … #define RK3399_POST_YUV2YUV_Y2R_COE … #define RK3399_POST_YUV2YUV_3X3_COE … #define RK3399_POST_YUV2YUV_R2Y_COE … #define RK3399_WIN0_YUV2YUV_Y2R … #define RK3399_WIN0_YUV2YUV_3X3 … #define RK3399_WIN0_YUV2YUV_R2Y … #define RK3399_WIN1_YUV2YUV_Y2R … #define RK3399_WIN1_YUV2YUV_3X3 … #define RK3399_WIN1_YUV2YUV_R2Y … #define RK3399_WIN2_YUV2YUV_Y2R … #define RK3399_WIN2_YUV2YUV_3X3 … #define RK3399_WIN2_YUV2YUV_R2Y … #define RK3399_WIN3_YUV2YUV_Y2R … #define RK3399_WIN3_YUV2YUV_3X3 … #define RK3399_WIN3_YUV2YUV_R2Y … #define RK3399_WIN2_LUT_ADDR … #define RK3399_WIN3_LUT_ADDR … #define RK3399_HWC_LUT_ADDR … #define RK3399_CABC_GAMMA_LUT_ADDR … #define RK3399_GAMMA_LUT_ADDR … /* rk3399 register definition end */ /* rk3328 register definition end */ #define RK3328_REG_CFG_DONE … #define RK3328_VERSION_INFO … #define RK3328_SYS_CTRL … #define RK3328_SYS_CTRL1 … #define RK3328_DSP_CTRL0 … #define RK3328_DSP_CTRL1 … #define RK3328_DSP_BG … #define RK3328_AUTO_GATING_EN … #define RK3328_LINE_FLAG … #define RK3328_VOP_STATUS … #define RK3328_BLANKING_VALUE … #define RK3328_WIN0_DSP_BG … #define RK3328_WIN1_DSP_BG … #define RK3328_DBG_PERF_LATENCY_CTRL0 … #define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 … #define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 … #define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 … #define RK3328_INTR_EN0 … #define RK3328_INTR_CLEAR0 … #define RK3328_INTR_STATUS0 … #define RK3328_INTR_RAW_STATUS0 … #define RK3328_INTR_EN1 … #define RK3328_INTR_CLEAR1 … #define RK3328_INTR_STATUS1 … #define RK3328_INTR_RAW_STATUS1 … #define RK3328_WIN0_CTRL0 … #define RK3328_WIN0_CTRL1 … #define RK3328_WIN0_COLOR_KEY … #define RK3328_WIN0_VIR … #define RK3328_WIN0_YRGB_MST … #define RK3328_WIN0_CBR_MST … #define RK3328_WIN0_ACT_INFO … #define RK3328_WIN0_DSP_INFO … #define RK3328_WIN0_DSP_ST … #define RK3328_WIN0_SCL_FACTOR_YRGB … #define RK3328_WIN0_SCL_FACTOR_CBR … #define RK3328_WIN0_SCL_OFFSET … #define RK3328_WIN0_SRC_ALPHA_CTRL … #define RK3328_WIN0_DST_ALPHA_CTRL … #define RK3328_WIN0_FADING_CTRL … #define RK3328_WIN0_CTRL2 … #define RK3328_DBG_WIN0_REG0 … #define RK3328_DBG_WIN0_REG1 … #define RK3328_DBG_WIN0_REG2 … #define RK3328_DBG_WIN0_RESERVED … #define RK3328_WIN1_CTRL0 … #define RK3328_WIN1_CTRL1 … #define RK3328_WIN1_COLOR_KEY … #define RK3328_WIN1_VIR … #define RK3328_WIN1_YRGB_MST … #define RK3328_WIN1_CBR_MST … #define RK3328_WIN1_ACT_INFO … #define RK3328_WIN1_DSP_INFO … #define RK3328_WIN1_DSP_ST … #define RK3328_WIN1_SCL_FACTOR_YRGB … #define RK3328_WIN1_SCL_FACTOR_CBR … #define RK3328_WIN1_SCL_OFFSET … #define RK3328_WIN1_SRC_ALPHA_CTRL … #define RK3328_WIN1_DST_ALPHA_CTRL … #define RK3328_WIN1_FADING_CTRL … #define RK3328_WIN1_CTRL2 … #define RK3328_DBG_WIN1_REG0 … #define RK3328_DBG_WIN1_REG1 … #define RK3328_DBG_WIN1_REG2 … #define RK3328_DBG_WIN1_RESERVED … #define RK3328_WIN2_CTRL0 … #define RK3328_WIN2_CTRL1 … #define RK3328_WIN2_COLOR_KEY … #define RK3328_WIN2_VIR … #define RK3328_WIN2_YRGB_MST … #define RK3328_WIN2_CBR_MST … #define RK3328_WIN2_ACT_INFO … #define RK3328_WIN2_DSP_INFO … #define RK3328_WIN2_DSP_ST … #define RK3328_WIN2_SCL_FACTOR_YRGB … #define RK3328_WIN2_SCL_FACTOR_CBR … #define RK3328_WIN2_SCL_OFFSET … #define RK3328_WIN2_SRC_ALPHA_CTRL … #define RK3328_WIN2_DST_ALPHA_CTRL … #define RK3328_WIN2_FADING_CTRL … #define RK3328_WIN2_CTRL2 … #define RK3328_DBG_WIN2_REG0 … #define RK3328_DBG_WIN2_REG1 … #define RK3328_DBG_WIN2_REG2 … #define RK3328_DBG_WIN2_RESERVED … #define RK3328_WIN3_CTRL0 … #define RK3328_WIN3_CTRL1 … #define RK3328_WIN3_COLOR_KEY … #define RK3328_WIN3_VIR … #define RK3328_WIN3_YRGB_MST … #define RK3328_WIN3_CBR_MST … #define RK3328_WIN3_ACT_INFO … #define RK3328_WIN3_DSP_INFO … #define RK3328_WIN3_DSP_ST … #define RK3328_WIN3_SCL_FACTOR_YRGB … #define RK3328_WIN3_SCL_FACTOR_CBR … #define RK3328_WIN3_SCL_OFFSET … #define RK3328_WIN3_SRC_ALPHA_CTRL … #define RK3328_WIN3_DST_ALPHA_CTRL … #define RK3328_WIN3_FADING_CTRL … #define RK3328_WIN3_CTRL2 … #define RK3328_DBG_WIN3_REG0 … #define RK3328_DBG_WIN3_REG1 … #define RK3328_DBG_WIN3_REG2 … #define RK3328_DBG_WIN3_RESERVED … #define RK3328_HWC_CTRL0 … #define RK3328_HWC_CTRL1 … #define RK3328_HWC_MST … #define RK3328_HWC_DSP_ST … #define RK3328_HWC_SRC_ALPHA_CTRL … #define RK3328_HWC_DST_ALPHA_CTRL … #define RK3328_HWC_FADING_CTRL … #define RK3328_HWC_RESERVED1 … #define RK3328_POST_DSP_HACT_INFO … #define RK3328_POST_DSP_VACT_INFO … #define RK3328_POST_SCL_FACTOR_YRGB … #define RK3328_POST_RESERVED … #define RK3328_POST_SCL_CTRL … #define RK3328_POST_DSP_VACT_INFO_F1 … #define RK3328_DSP_HTOTAL_HS_END … #define RK3328_DSP_HACT_ST_END … #define RK3328_DSP_VTOTAL_VS_END … #define RK3328_DSP_VACT_ST_END … #define RK3328_DSP_VS_ST_END_F1 … #define RK3328_DSP_VACT_ST_END_F1 … #define RK3328_BCSH_COLOR_BAR … #define RK3328_BCSH_BCS … #define RK3328_BCSH_H … #define RK3328_BCSH_CTRL … #define RK3328_FRC_LOWER01_0 … #define RK3328_FRC_LOWER01_1 … #define RK3328_FRC_LOWER10_0 … #define RK3328_FRC_LOWER10_1 … #define RK3328_FRC_LOWER11_0 … #define RK3328_FRC_LOWER11_1 … #define RK3328_DBG_POST_REG0 … #define RK3328_DBG_POST_RESERVED … #define RK3328_DBG_DATAO … #define RK3328_DBG_DATAO_2 … /* sdr to hdr */ #define RK3328_SDR2HDR_CTRL … #define RK3328_EOTF_OETF_Y0 … #define RK3328_RESERVED0001 … #define RK3328_RESERVED0002 … #define RK3328_EOTF_OETF_Y1 … #define RK3328_EOTF_OETF_Y64 … #define RK3328_OETF_DX_DXPOW1 … #define RK3328_OETF_DX_DXPOW64 … #define RK3328_OETF_XN1 … #define RK3328_OETF_XN63 … /* hdr to sdr */ #define RK3328_HDR2SDR_CTRL … #define RK3328_HDR2SDR_SRC_RANGE … #define RK3328_HDR2SDR_NORMFACEETF … #define RK3328_RESERVED0003 … #define RK3328_HDR2SDR_DST_RANGE … #define RK3328_HDR2SDR_NORMFACCGAMMA … #define RK3328_EETF_OETF_Y0 … #define RK3328_SAT_Y0 … #define RK3328_EETF_OETF_Y1 … #define RK3328_SAT_Y1 … #define RK3328_SAT_Y8 … #define RK3328_HWC_LUT_ADDR … /* rk3036 register definition */ #define RK3036_SYS_CTRL … #define RK3036_DSP_CTRL0 … #define RK3036_DSP_CTRL1 … #define RK3036_INT_STATUS … #define RK3036_ALPHA_CTRL … #define RK3036_WIN0_COLOR_KEY … #define RK3036_WIN1_COLOR_KEY … #define RK3036_WIN0_YRGB_MST … #define RK3036_WIN0_CBR_MST … #define RK3036_WIN1_VIR … #define RK3036_AXI_BUS_CTRL … #define RK3036_WIN0_VIR … #define RK3036_WIN0_ACT_INFO … #define RK3036_WIN0_DSP_INFO … #define RK3036_WIN0_DSP_ST … #define RK3036_WIN0_SCL_FACTOR_YRGB … #define RK3036_WIN0_SCL_FACTOR_CBR … #define RK3036_WIN0_SCL_OFFSET … #define RK3036_HWC_MST … #define RK3036_HWC_DSP_ST … #define RK3036_DSP_HTOTAL_HS_END … #define RK3036_DSP_HACT_ST_END … #define RK3036_DSP_VTOTAL_VS_END … #define RK3036_DSP_VACT_ST_END … #define RK3036_DSP_VS_ST_END_F1 … #define RK3036_DSP_VACT_ST_END_F1 … #define RK3036_GATHER_TRANSFER … #define RK3036_VERSION_INFO … #define RK3036_REG_CFG_DONE … #define RK3036_WIN1_MST … #define RK3036_WIN1_ACT_INFO … #define RK3036_WIN1_DSP_INFO … #define RK3036_WIN1_DSP_ST … #define RK3036_WIN1_SCL_FACTOR_YRGB … #define RK3036_WIN1_SCL_OFFSET … #define RK3036_BCSH_CTRL … #define RK3036_BCSH_COLOR_BAR … #define RK3036_BCSH_BCS … #define RK3036_BCSH_H … #define RK3036_WIN1_LUT_ADDR … #define RK3036_HWC_LUT_ADDR … /* rk3036 register definition end */ /* rk3126 register definition */ #define RK3126_INT_SCALER … /* win1 register */ #define RK3126_WIN1_MST … #define RK3126_WIN1_DSP_INFO … #define RK3126_WIN1_DSP_ST … /* rk3126 register definition end */ /* px30 register definition */ #define PX30_REG_CFG_DONE … #define PX30_VERSION … #define PX30_DSP_BG … #define PX30_MCU_CTRL … #define PX30_SYS_CTRL0 … #define PX30_SYS_CTRL1 … #define PX30_SYS_CTRL2 … #define PX30_DSP_CTRL0 … #define PX30_DSP_CTRL2 … #define PX30_VOP_STATUS … #define PX30_LINE_FLAG … #define PX30_INTR_EN … #define PX30_INTR_CLEAR … #define PX30_INTR_STATUS … #define PX30_WIN0_CTRL0 … #define PX30_WIN0_CTRL1 … #define PX30_WIN0_COLOR_KEY … #define PX30_WIN0_VIR … #define PX30_WIN0_YRGB_MST0 … #define PX30_WIN0_CBR_MST0 … #define PX30_WIN0_ACT_INFO … #define PX30_WIN0_DSP_INFO … #define PX30_WIN0_DSP_ST … #define PX30_WIN0_SCL_FACTOR_YRGB … #define PX30_WIN0_SCL_FACTOR_CBR … #define PX30_WIN0_SCL_OFFSET … #define PX30_WIN0_ALPHA_CTRL … #define PX30_WIN1_CTRL0 … #define PX30_WIN1_CTRL1 … #define PX30_WIN1_VIR … #define PX30_WIN1_MST … #define PX30_WIN1_DSP_INFO … #define PX30_WIN1_DSP_ST … #define PX30_WIN1_COLOR_KEY … #define PX30_WIN1_ALPHA_CTRL … #define PX30_HWC_CTRL0 … #define PX30_HWC_CTRL1 … #define PX30_HWC_MST … #define PX30_HWC_DSP_ST … #define PX30_HWC_ALPHA_CTRL … #define PX30_DSP_HTOTAL_HS_END … #define PX30_DSP_HACT_ST_END … #define PX30_DSP_VTOTAL_VS_END … #define PX30_DSP_VACT_ST_END … #define PX30_DSP_VS_ST_END_F1 … #define PX30_DSP_VACT_ST_END_F1 … #define PX30_BCSH_CTRL … #define PX30_BCSH_COL_BAR … #define PX30_BCSH_BCS … #define PX30_BCSH_H … #define PX30_FRC_LOWER01_0 … #define PX30_FRC_LOWER01_1 … #define PX30_FRC_LOWER10_0 … #define PX30_FRC_LOWER10_1 … #define PX30_FRC_LOWER11_0 … #define PX30_FRC_LOWER11_1 … #define PX30_MCU_RW_BYPASS_PORT … #define PX30_WIN2_CTRL0 … #define PX30_WIN2_CTRL1 … #define PX30_WIN2_VIR0_1 … #define PX30_WIN2_VIR2_3 … #define PX30_WIN2_MST0 … #define PX30_WIN2_DSP_INFO0 … #define PX30_WIN2_DSP_ST0 … #define PX30_WIN2_COLOR_KEY … #define PX30_WIN2_ALPHA_CTRL … #define PX30_BLANKING_VALUE … #define PX30_FLAG_REG_FRM_VALID … #define PX30_FLAG_REG … #define PX30_HWC_LUT_ADDR … #define PX30_GAMMA_LUT_ADDR … /* px30 register definition end */ /* rk3188 register definition */ #define RK3188_SYS_CTRL … #define RK3188_DSP_CTRL0 … #define RK3188_DSP_CTRL1 … #define RK3188_INT_STATUS … #define RK3188_ALPHA_CTRL … #define RK3188_WIN0_YRGB_MST0 … #define RK3188_WIN0_CBR_MST0 … #define RK3188_WIN0_YRGB_MST1 … #define RK3188_WIN0_CBR_MST1 … #define RK3188_WIN_VIR … #define RK3188_WIN0_ACT_INFO … #define RK3188_WIN0_DSP_INFO … #define RK3188_WIN0_DSP_ST … #define RK3188_WIN0_SCL_FACTOR_YRGB … #define RK3188_WIN0_SCL_FACTOR_CBR … #define RK3188_WIN1_MST … #define RK3188_WIN1_DSP_INFO … #define RK3188_WIN1_DSP_ST … #define RK3188_DSP_HTOTAL_HS_END … #define RK3188_DSP_HACT_ST_END … #define RK3188_DSP_VTOTAL_VS_END … #define RK3188_DSP_VACT_ST_END … #define RK3188_REG_CFG_DONE … /* rk3188 register definition end */ /* rk3066 register definition */ #define RK3066_SYS_CTRL0 … #define RK3066_SYS_CTRL1 … #define RK3066_DSP_CTRL0 … #define RK3066_DSP_CTRL1 … #define RK3066_INT_STATUS … #define RK3066_MCU_CTRL … #define RK3066_BLEND_CTRL … #define RK3066_WIN0_COLOR_KEY_CTRL … #define RK3066_WIN1_COLOR_KEY_CTRL … #define RK3066_WIN2_COLOR_KEY_CTRL … #define RK3066_WIN0_YRGB_MST0 … #define RK3066_WIN0_CBR_MST0 … #define RK3066_WIN0_YRGB_MST1 … #define RK3066_WIN0_CBR_MST1 … #define RK3066_WIN0_VIR … #define RK3066_WIN0_ACT_INFO … #define RK3066_WIN0_DSP_INFO … #define RK3066_WIN0_DSP_ST … #define RK3066_WIN0_SCL_FACTOR_YRGB … #define RK3066_WIN0_SCL_FACTOR_CBR … #define RK3066_WIN0_SCL_OFFSET … #define RK3066_WIN1_YRGB_MST … #define RK3066_WIN1_CBR_MST … #define RK3066_WIN1_VIR … #define RK3066_WIN1_ACT_INFO … #define RK3066_WIN1_DSP_INFO … #define RK3066_WIN1_DSP_ST … #define RK3066_WIN1_SCL_FACTOR_YRGB … #define RK3066_WIN1_SCL_FACTOR_CBR … #define RK3066_WIN1_SCL_OFFSET … #define RK3066_WIN2_MST … #define RK3066_WIN2_VIR … #define RK3066_WIN2_DSP_INFO … #define RK3066_WIN2_DSP_ST … #define RK3066_HWC_MST … #define RK3066_HWC_DSP_ST … #define RK3066_HWC_COLOR_LUT0 … #define RK3066_HWC_COLOR_LUT1 … #define RK3066_HWC_COLOR_LUT2 … #define RK3066_DSP_HTOTAL_HS_END … #define RK3066_DSP_HACT_ST_END … #define RK3066_DSP_VTOTAL_VS_END … #define RK3066_DSP_VACT_ST_END … #define RK3066_DSP_VS_ST_END_F1 … #define RK3066_DSP_VACT_ST_END_F1 … #define RK3066_REG_CFG_DONE … #define RK3066_MCU_BYPASS_WPORT … #define RK3066_MCU_BYPASS_RPORT … #define RK3066_WIN2_LUT_ADDR … #define RK3066_DSP_LUT_ADDR … /* rk3066 register definition end */ #endif /* _ROCKCHIP_VOP_REG_H */
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