// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author: * Chris Zhong <[email protected]> * Nickey Yang <[email protected]> */ #include <linux/clk.h> #include <linux/iopoll.h> #include <linux/math64.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/of_platform.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <video/mipi_display.h> #include <drm/bridge/dw_mipi_dsi.h> #include <drm/drm_mipi_dsi.h> #include <drm/drm_of.h> #include <drm/drm_simple_kms_helper.h> #include "rockchip_drm_drv.h" #define DSI_PHY_RSTZ … #define PHY_DISFORCEPLL … #define PHY_ENFORCEPLL … #define PHY_DISABLECLK … #define PHY_ENABLECLK … #define PHY_RSTZ … #define PHY_UNRSTZ … #define PHY_SHUTDOWNZ … #define PHY_UNSHUTDOWNZ … #define DSI_PHY_IF_CFG … #define N_LANES(n) … #define PHY_STOP_WAIT_TIME(cycle) … #define DSI_PHY_STATUS … #define LOCK … #define STOP_STATE_CLK_LANE … #define DSI_PHY_TST_CTRL0 … #define PHY_TESTCLK … #define PHY_UNTESTCLK … #define PHY_TESTCLR … #define PHY_UNTESTCLR … #define DSI_PHY_TST_CTRL1 … #define PHY_TESTEN … #define PHY_UNTESTEN … #define PHY_TESTDOUT(n) … #define PHY_TESTDIN(n) … #define DSI_INT_ST0 … #define DSI_INT_ST1 … #define DSI_INT_MSK0 … #define DSI_INT_MSK1 … #define PHY_STATUS_TIMEOUT_US … #define CMD_PKT_STATUS_TIMEOUT_US … #define BYPASS_VCO_RANGE … #define VCO_RANGE_CON_SEL(val) … #define VCO_IN_CAP_CON_DEFAULT … #define VCO_IN_CAP_CON_LOW … #define VCO_IN_CAP_CON_HIGH … #define REF_BIAS_CUR_SEL … #define CP_CURRENT_3UA … #define CP_CURRENT_4_5UA … #define CP_CURRENT_7_5UA … #define CP_CURRENT_6UA … #define CP_CURRENT_12UA … #define CP_CURRENT_SEL(val) … #define CP_PROGRAM_EN … #define LPF_RESISTORS_15_5KOHM … #define LPF_RESISTORS_13KOHM … #define LPF_RESISTORS_11_5KOHM … #define LPF_RESISTORS_10_5KOHM … #define LPF_RESISTORS_8KOHM … #define LPF_PROGRAM_EN … #define LPF_RESISTORS_SEL(val) … #define HSFREQRANGE_SEL(val) … #define INPUT_DIVIDER(val) … #define LOW_PROGRAM_EN … #define HIGH_PROGRAM_EN … #define LOOP_DIV_LOW_SEL(val) … #define LOOP_DIV_HIGH_SEL(val) … #define PLL_LOOP_DIV_EN … #define PLL_INPUT_DIV_EN … #define POWER_CONTROL … #define INTERNAL_REG_CURRENT … #define BIAS_BLOCK_ON … #define BANDGAP_ON … #define TER_RESISTOR_HIGH … #define TER_RESISTOR_LOW … #define LEVEL_SHIFTERS_ON … #define TER_CAL_DONE … #define SETRD_MAX … #define POWER_MANAGE … #define TER_RESISTORS_ON … #define BIASEXTR_SEL(val) … #define BANDGAP_SEL(val) … #define TLP_PROGRAM_EN … #define THS_PRE_PROGRAM_EN … #define THS_ZERO_PROGRAM_EN … #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL … #define PLL_CP_CONTROL_PLL_LOCK_BYPASS … #define PLL_LPF_AND_CP_CONTROL … #define PLL_INPUT_DIVIDER_RATIO … #define PLL_LOOP_DIVIDER_RATIO … #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL … #define BANDGAP_AND_BIAS_CONTROL … #define TERMINATION_RESISTER_CONTROL … #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY … #define HS_RX_CONTROL_OF_LANE_CLK … #define HS_RX_CONTROL_OF_LANE_0 … #define HS_RX_CONTROL_OF_LANE_1 … #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL … #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL … #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL … #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL … #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL … #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL … #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL … #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL … #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL … #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL … #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL … #define HS_RX_DATA_LANE_THS_SETTLE_CONTROL … #define HS_RX_CONTROL_OF_LANE_2 … #define HS_RX_CONTROL_OF_LANE_3 … #define DW_MIPI_NEEDS_PHY_CFG_CLK … #define DW_MIPI_NEEDS_GRF_CLK … #define PX30_GRF_PD_VO_CON1 … #define PX30_DSI_FORCETXSTOPMODE … #define PX30_DSI_FORCERXMODE … #define PX30_DSI_TURNDISABLE … #define PX30_DSI_LCDC_SEL … #define RK3128_GRF_LVDS_CON0 … #define RK3128_DSI_FORCETXSTOPMODE … #define RK3128_DSI_FORCERXMODE … #define RK3128_DSI_TURNDISABLE … #define RK3288_GRF_SOC_CON6 … #define RK3288_DSI0_LCDC_SEL … #define RK3288_DSI1_LCDC_SEL … #define RK3399_GRF_SOC_CON20 … #define RK3399_DSI0_LCDC_SEL … #define RK3399_DSI1_LCDC_SEL … #define RK3399_GRF_SOC_CON22 … #define RK3399_DSI0_TURNREQUEST … #define RK3399_DSI0_TURNDISABLE … #define RK3399_DSI0_FORCETXSTOPMODE … #define RK3399_DSI0_FORCERXMODE … #define RK3399_GRF_SOC_CON23 … #define RK3399_DSI1_TURNDISABLE … #define RK3399_DSI1_FORCETXSTOPMODE … #define RK3399_DSI1_FORCERXMODE … #define RK3399_DSI1_ENABLE … #define RK3399_GRF_SOC_CON24 … #define RK3399_TXRX_MASTERSLAVEZ … #define RK3399_TXRX_ENABLECLK … #define RK3399_TXRX_BASEDIR … #define RK3399_TXRX_SRC_SEL_ISP0 … #define RK3399_TXRX_TURNREQUEST … #define RK3568_GRF_VO_CON2 … #define RK3568_DSI0_SKEWCALHS … #define RK3568_DSI0_FORCETXSTOPMODE … #define RK3568_DSI0_TURNDISABLE … #define RK3568_DSI0_FORCERXMODE … /* * Note these registers do not appear in the datasheet, they are * however present in the BSP driver which is where these values * come from. Name GRF_VO_CON3 is assumed. */ #define RK3568_GRF_VO_CON3 … #define RK3568_DSI1_SKEWCALHS … #define RK3568_DSI1_FORCETXSTOPMODE … #define RK3568_DSI1_TURNDISABLE … #define RK3568_DSI1_FORCERXMODE … #define RV1126_GRF_DSIPHY_CON … #define RV1126_DSI_FORCETXSTOPMODE … #define RV1126_DSI_TURNDISABLE … #define RV1126_DSI_FORCERXMODE … #define HIWORD_UPDATE(val, mask) … enum { … }; enum { … }; enum { … }; struct rockchip_dw_dsi_chip_data { … }; struct dw_mipi_dsi_rockchip { … }; static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder) { … } struct dphy_pll_parameter_map { … }; /* The table is based on 27MHz DPHY pll reference clock. */ static const struct dphy_pll_parameter_map dppa_map[] = …; static int max_mbps_to_parameter(unsigned int max_mbps) { … } static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) { … } static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, u8 test_code, u8 test_data) { … } /* * ns2bc - Nanoseconds to byte clock cycles */ static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) { … } /* * ns2ui - Nanoseconds to UI time periods */ static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) { … } static int dw_mipi_dsi_phy_init(void *priv_data) { … } static void dw_mipi_dsi_phy_power_on(void *priv_data) { … } static void dw_mipi_dsi_phy_power_off(void *priv_data) { … } static int dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, unsigned long mode_flags, u32 lanes, u32 format, unsigned int *lane_mbps) { … } struct hstt { … }; #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) … /* Table A-3 High-Speed Transition Times */ static struct hstt hstt_table[] = …; static int dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, struct dw_mipi_dsi_dphy_timing *timing) { … } static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = …; static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) { … } static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, int mux) { … } static int dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { … } static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) { … } static const struct drm_encoder_helper_funcs dw_mipi_dsi_encoder_helper_funcs = …; static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, struct drm_device *drm_dev) { … } static struct device *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) { … } static int dw_mipi_dsi_rockchip_bind(struct device *dev, struct device *master, void *data) { … } static void dw_mipi_dsi_rockchip_unbind(struct device *dev, struct device *master, void *data) { … } static const struct component_ops dw_mipi_dsi_rockchip_ops = …; static int dw_mipi_dsi_rockchip_host_attach(void *priv_data, struct mipi_dsi_device *device) { … } static int dw_mipi_dsi_rockchip_host_detach(void *priv_data, struct mipi_dsi_device *device) { … } static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = …; static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev, struct device *master, void *data) { … } static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev, struct device *master, void *data) { … } static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = …; static int dw_mipi_dsi_dphy_init(struct phy *phy) { … } static int dw_mipi_dsi_dphy_exit(struct phy *phy) { … } static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts) { … } static int dw_mipi_dsi_dphy_power_on(struct phy *phy) { … } static int dw_mipi_dsi_dphy_power_off(struct phy *phy) { … } static const struct phy_ops dw_mipi_dsi_dphy_ops = …; static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev) { … } static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = …; static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) { … } static void dw_mipi_dsi_rockchip_remove(struct platform_device *pdev) { … } static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = …; static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = …; static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = …; static int rk3399_dphy_tx1rx1_init(struct phy *phy) { … } static int rk3399_dphy_tx1rx1_power_on(struct phy *phy) { … } static int rk3399_dphy_tx1rx1_power_off(struct phy *phy) { … } static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = …; static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = …; static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = …; static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = …; MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids); struct platform_driver dw_mipi_dsi_rockchip_driver = …;
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