/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Zheng Yang <[email protected]> */ #ifndef __RK3066_HDMI_H__ #define __RK3066_HDMI_H__ #define GRF_SOC_CON0 … #define HDMI_VIDEO_SEL … #define DDC_SEGMENT_ADDR … #define HDMI_SCL_RATE … #define HDMI_MAXIMUM_INFO_FRAME_SIZE … #define N_32K … #define N_441K … #define N_882K … #define N_1764K … #define N_48K … #define N_96K … #define N_192K … #define HDMI_SYS_CTRL … #define HDMI_LR_SWAP_N3 … #define HDMI_N2 … #define HDMI_N1 … #define HDMI_SPDIF_FS_CTS_INT3 … #define HDMI_CTS_INT2 … #define HDMI_CTS_INT1 … #define HDMI_CTS_EXT3 … #define HDMI_CTS_EXT2 … #define HDMI_CTS_EXT1 … #define HDMI_AUDIO_CTRL1 … #define HDMI_AUDIO_CTRL2 … #define HDMI_I2S_AUDIO_CTRL … #define HDMI_I2S_SWAP … #define HDMI_AUDIO_STA_BIT_CTRL1 … #define HDMI_AUDIO_STA_BIT_CTRL2 … #define HDMI_AUDIO_SRC_NUM_AND_LENGTH … #define HDMI_AV_CTRL1 … #define HDMI_VIDEO_CTRL1 … #define HDMI_DEEP_COLOR_MODE … #define HDMI_EXT_VIDEO_PARA … #define HDMI_EXT_HTOTAL_L … #define HDMI_EXT_HTOTAL_H … #define HDMI_EXT_HBLANK_L … #define HDMI_EXT_HBLANK_H … #define HDMI_EXT_HDELAY_L … #define HDMI_EXT_HDELAY_H … #define HDMI_EXT_HDURATION_L … #define HDMI_EXT_HDURATION_H … #define HDMI_EXT_VTOTAL_L … #define HDMI_EXT_VTOTAL_H … #define HDMI_AV_CTRL2 … #define HDMI_EXT_VBLANK_L … #define HDMI_EXT_VBLANK_H … #define HDMI_EXT_VDELAY … #define HDMI_EXT_VDURATION … #define HDMI_CP_MANU_SEND_CTRL … #define HDMI_CP_AUTO_SEND_CTRL … #define HDMI_AUTO_CHECKSUM_OPT … #define HDMI_VIDEO_CTRL2 … #define HDMI_PHY_OPTION … #define HDMI_CP_BUF_INDEX … #define HDMI_CP_BUF_ACC_HB0 … #define HDMI_CP_BUF_ACC_HB1 … #define HDMI_CP_BUF_ACC_HB2 … #define HDMI_CP_BUF_ACC_PB0 … #define HDMI_DDC_READ_FIFO_ADDR … #define HDMI_DDC_BUS_FREQ_L … #define HDMI_DDC_BUS_FREQ_H … #define HDMI_DDC_BUS_CTRL … #define HDMI_DDC_I2C_LEN … #define HDMI_DDC_I2C_OFFSET … #define HDMI_DDC_I2C_CTRL … #define HDMI_DDC_I2C_READ_BUF0 … #define HDMI_DDC_I2C_READ_BUF1 … #define HDMI_DDC_I2C_READ_BUF2 … #define HDMI_DDC_I2C_READ_BUF3 … #define HDMI_DDC_I2C_WRITE_BUF0 … #define HDMI_DDC_I2C_WRITE_BUF1 … #define HDMI_DDC_I2C_WRITE_BUF2 … #define HDMI_DDC_I2C_WRITE_BUF3 … #define HDMI_DDC_I2C_WRITE_BUF4 … #define HDMI_DDC_I2C_WRITE_BUF5 … #define HDMI_DDC_I2C_WRITE_BUF6 … #define HDMI_INTR_MASK1 … #define HDMI_INTR_MASK2 … #define HDMI_INTR_STATUS1 … #define HDMI_INTR_STATUS2 … #define HDMI_INTR_MASK3 … #define HDMI_INTR_MASK4 … #define HDMI_INTR_STATUS3 … #define HDMI_INTR_STATUS4 … #define HDMI_HDCP_CTRL … #define HDMI_EDID_SEGMENT_POINTER … #define HDMI_EDID_WORD_ADDR … #define HDMI_EDID_FIFO_ADDR … #define HDMI_HPG_MENS_STA … #define HDMI_INTERNAL_CLK_DIVIDER … enum { … }; #endif /* __RK3066_HDMI_H__ */
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