/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2009, Intel Corporation. */ #ifndef __PSB_INTEL_REG_H__ #define __PSB_INTEL_REG_H__ /* * GPIO regs */ #define GPIOA … #define GPIOB … #define GPIOC … #define GPIOD … #define GPIOE … #define GPIOF … #define GPIOG … #define GPIOH … #define GPIO_CLOCK_DIR_MASK … #define GPIO_CLOCK_DIR_IN … #define GPIO_CLOCK_DIR_OUT … #define GPIO_CLOCK_VAL_MASK … #define GPIO_CLOCK_VAL_OUT … #define GPIO_CLOCK_VAL_IN … #define GPIO_CLOCK_PULLUP_DISABLE … #define GPIO_DATA_DIR_MASK … #define GPIO_DATA_DIR_IN … #define GPIO_DATA_DIR_OUT … #define GPIO_DATA_VAL_MASK … #define GPIO_DATA_VAL_OUT … #define GPIO_DATA_VAL_IN … #define GPIO_DATA_PULLUP_DISABLE … #define GMBUS0 … #define GMBUS_RATE_100KHZ … #define GMBUS_RATE_50KHZ … #define GMBUS_RATE_400KHZ … #define GMBUS_RATE_1MHZ … #define GMBUS_HOLD_EXT … #define GMBUS_PORT_DISABLED … #define GMBUS_PORT_SSC … #define GMBUS_PORT_VGADDC … #define GMBUS_PORT_PANEL … #define GMBUS_PORT_DPC … #define GMBUS_PORT_DPB … /* 6 reserved */ #define GMBUS_PORT_DPD … #define GMBUS_NUM_PORTS … #define GMBUS1 … #define GMBUS_SW_CLR_INT … #define GMBUS_SW_RDY … #define GMBUS_ENT … #define GMBUS_CYCLE_NONE … #define GMBUS_CYCLE_WAIT … #define GMBUS_CYCLE_INDEX … #define GMBUS_CYCLE_STOP … #define GMBUS_BYTE_COUNT_SHIFT … #define GMBUS_SLAVE_INDEX_SHIFT … #define GMBUS_SLAVE_ADDR_SHIFT … #define GMBUS_SLAVE_READ … #define GMBUS_SLAVE_WRITE … #define GMBUS2 … #define GMBUS_INUSE … #define GMBUS_HW_WAIT_PHASE … #define GMBUS_STALL_TIMEOUT … #define GMBUS_INT … #define GMBUS_HW_RDY … #define GMBUS_SATOER … #define GMBUS_ACTIVE … #define GMBUS3 … #define GMBUS4 … #define GMBUS_SLAVE_TIMEOUT_EN … #define GMBUS_NAK_EN … #define GMBUS_IDLE_EN … #define GMBUS_HW_WAIT_EN … #define GMBUS_HW_RDY_EN … #define GMBUS5 … #define GMBUS_2BYTE_INDEX_EN … #define BLC_PWM_CTL … #define BLC_PWM_CTL2 … #define PWM_ENABLE … #define PWM_LEGACY_MODE … #define PWM_PIPE_B … #define BLC_PWM_CTL_C … #define BLC_PWM_CTL2_C … #define BACKLIGHT_MODULATION_FREQ_SHIFT … /* * This is the most significant 15 bits of the number of backlight cycles in a * complete cycle of the modulated backlight control. * * The actual value is this field multiplied by two. */ #define BACKLIGHT_MODULATION_FREQ_MASK … #define BLM_LEGACY_MODE … /* * This is the number of cycles out of the backlight modulation cycle for which * the backlight is on. * * This field must be no greater than the number of cycles in the complete * backlight modulation cycle. */ #define BACKLIGHT_DUTY_CYCLE_SHIFT … #define BACKLIGHT_DUTY_CYCLE_MASK … #define I915_GCFGC … #define I915_LOW_FREQUENCY_ENABLE … #define I915_DISPLAY_CLOCK_190_200_MHZ … #define I915_DISPLAY_CLOCK_333_MHZ … #define I915_DISPLAY_CLOCK_MASK … #define I855_HPLLCC … #define I855_CLOCK_CONTROL_MASK … #define I855_CLOCK_133_200 … #define I855_CLOCK_100_200 … #define I855_CLOCK_100_133 … #define I855_CLOCK_166_250 … /* I830 CRTC registers */ #define HTOTAL_A … #define HBLANK_A … #define HSYNC_A … #define VTOTAL_A … #define VBLANK_A … #define VSYNC_A … #define PIPEASRC … #define BCLRPAT_A … #define VSYNCSHIFT_A … #define HTOTAL_B … #define HBLANK_B … #define HSYNC_B … #define VTOTAL_B … #define VBLANK_B … #define VSYNC_B … #define PIPEBSRC … #define BCLRPAT_B … #define VSYNCSHIFT_B … #define HTOTAL_C … #define HBLANK_C … #define HSYNC_C … #define VTOTAL_C … #define VBLANK_C … #define VSYNC_C … #define PIPECSRC … #define BCLRPAT_C … #define VSYNCSHIFT_C … #define PP_STATUS … #define PP_ON … /* * Indicates that all dependencies of the panel are on: * * - PLL enabled * - pipe enabled * - LVDS/DVOB/DVOC on */ #define PP_READY … #define PP_SEQUENCE_NONE … #define PP_SEQUENCE_ON … #define PP_SEQUENCE_OFF … #define PP_SEQUENCE_MASK … #define PP_CYCLE_DELAY_ACTIVE … #define PP_SEQUENCE_STATE_ON_IDLE … #define PP_SEQUENCE_STATE_MASK … #define PP_CONTROL … #define POWER_TARGET_ON … #define PANEL_UNLOCK_REGS … #define PANEL_UNLOCK_MASK … #define EDP_FORCE_VDD … #define EDP_BLC_ENABLE … #define PANEL_POWER_RESET … #define PANEL_POWER_OFF … #define PANEL_POWER_ON … /* Poulsbo/Oaktrail */ #define LVDSPP_ON … #define LVDSPP_OFF … #define PP_CYCLE … /* Cedartrail */ #define PP_ON_DELAYS … #define PANEL_PORT_SELECT_MASK … #define PANEL_PORT_SELECT_LVDS … #define PANEL_PORT_SELECT_EDP … #define PANEL_POWER_UP_DELAY_MASK … #define PANEL_POWER_UP_DELAY_SHIFT … #define PANEL_LIGHT_ON_DELAY_MASK … #define PANEL_LIGHT_ON_DELAY_SHIFT … #define PP_OFF_DELAYS … #define PANEL_POWER_DOWN_DELAY_MASK … #define PANEL_POWER_DOWN_DELAY_SHIFT … #define PANEL_LIGHT_OFF_DELAY_MASK … #define PANEL_LIGHT_OFF_DELAY_SHIFT … #define PP_DIVISOR … #define PP_REFERENCE_DIVIDER_MASK … #define PP_REFERENCE_DIVIDER_SHIFT … #define PANEL_POWER_CYCLE_DELAY_MASK … #define PANEL_POWER_CYCLE_DELAY_SHIFT … #define PFIT_CONTROL … #define PFIT_ENABLE … #define PFIT_PIPE_MASK … #define PFIT_PIPE_SHIFT … #define PFIT_SCALING_MODE_PILLARBOX … #define PFIT_SCALING_MODE_LETTERBOX … #define VERT_INTERP_DISABLE … #define VERT_INTERP_BILINEAR … #define VERT_INTERP_MASK … #define VERT_AUTO_SCALE … #define HORIZ_INTERP_DISABLE … #define HORIZ_INTERP_BILINEAR … #define HORIZ_INTERP_MASK … #define HORIZ_AUTO_SCALE … #define PANEL_8TO6_DITHER_ENABLE … #define PFIT_PGM_RATIOS … #define PFIT_VERT_SCALE_MASK … #define PFIT_HORIZ_SCALE_MASK … #define PFIT_AUTO_RATIOS … #define DPLL_A … #define DPLL_B … #define DPLL_VCO_ENABLE … #define DPLL_DVO_HIGH_SPEED … #define DPLL_SYNCLOCK_ENABLE … #define DPLL_VGA_MODE_DIS … #define DPLLB_MODE_DAC_SERIAL … #define DPLLB_MODE_LVDS … #define DPLL_MODE_MASK … #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 … #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 … #define DPLLB_LVDS_P2_CLOCK_DIV_14 … #define DPLLB_LVDS_P2_CLOCK_DIV_7 … #define DPLL_P2_CLOCK_DIV_MASK … #define DPLL_FPA0h1_P1_POST_DIV_MASK … #define DPLL_LOCK … /* * The i830 generation, in DAC/serial mode, defines p1 as two plus this * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. */ #define DPLL_FPA01_P1_POST_DIV_MASK_I830 … /* * The i830 generation, in LVDS mode, defines P1 as the bit number set within * this field (only one bit may be set). */ #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS … #define DPLL_FPA01_P1_POST_DIV_SHIFT … #define PLL_P2_DIVIDE_BY_4 … #define PLL_P1_DIVIDE_BY_TWO … #define PLL_REF_INPUT_DREFCLK … #define PLL_REF_INPUT_TVCLKINA … #define PLL_REF_INPUT_TVCLKINBC … #define PLLB_REF_INPUT_SPREADSPECTRUMIN … #define PLL_REF_INPUT_MASK … #define PLL_LOAD_PULSE_PHASE_SHIFT … /* * Parallel to Serial Load Pulse phase selection. * Selects the phase for the 10X DPLL clock for the PCIe * digital display port. The range is 4 to 13; 10 or more * is just a flip delay. The default is 6 */ #define PLL_LOAD_PULSE_PHASE_MASK … #define DISPLAY_RATE_SELECT_FPA1 … /* * SDVO multiplier for 945G/GM. Not used on 965. * * DPLL_MD_UDI_MULTIPLIER_MASK */ #define SDVO_MULTIPLIER_MASK … #define SDVO_MULTIPLIER_SHIFT_HIRES … #define SDVO_MULTIPLIER_SHIFT_VGA … /* * PLL_MD */ /* Pipe A SDVO/UDI clock multiplier/divider register for G965. */ #define DPLL_A_MD … /* Pipe B SDVO/UDI clock multiplier/divider register for G965. */ #define DPLL_B_MD … /* * UDI pixel divider, controlling how many pixels are stuffed into a packet. * * Value is pixels minus 1. Must be set to 1 pixel for SDVO. */ #define DPLL_MD_UDI_DIVIDER_MASK … #define DPLL_MD_UDI_DIVIDER_SHIFT … /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ #define DPLL_MD_VGA_UDI_DIVIDER_MASK … #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT … /* * SDVO/UDI pixel multiplier. * * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus * clock rate is 10 times the DPLL clock. At low resolution/refresh rate * modes, the bus rate would be below the limits, so SDVO allows for stuffing * dummy bytes in the datastream at an increased clock rate, with both sides of * the link knowing how many bytes are fill. * * So, for a mode with a dotclock of 65Mhz, we would want to double the clock * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be * set to 130Mhz, and the SDVO multiplier set to 2x in this register and * through an SDVO command. * * This register field has values of multiplication factor minus 1, with * a maximum multiplier of 5 for SDVO. */ #define DPLL_MD_UDI_MULTIPLIER_MASK … #define DPLL_MD_UDI_MULTIPLIER_SHIFT … /* * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. * This best be set to the default value (3) or the CRT won't work. No, * I don't entirely understand what this does... */ #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK … #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT … #define DPLL_TEST … #define DPLLB_TEST_SDVO_DIV_1 … #define DPLLB_TEST_SDVO_DIV_2 … #define DPLLB_TEST_SDVO_DIV_4 … #define DPLLB_TEST_SDVO_DIV_MASK … #define DPLLB_TEST_N_BYPASS … #define DPLLB_TEST_M_BYPASS … #define DPLLB_INPUT_BUFFER_ENABLE … #define DPLLA_TEST_N_BYPASS … #define DPLLA_TEST_M_BYPASS … #define DPLLA_INPUT_BUFFER_ENABLE … #define ADPA … #define ADPA_DAC_ENABLE … #define ADPA_DAC_DISABLE … #define ADPA_PIPE_SELECT_MASK … #define ADPA_PIPE_A_SELECT … #define ADPA_PIPE_B_SELECT … #define ADPA_USE_VGA_HVPOLARITY … #define ADPA_SETS_HVPOLARITY … #define ADPA_VSYNC_CNTL_DISABLE … #define ADPA_VSYNC_CNTL_ENABLE … #define ADPA_HSYNC_CNTL_DISABLE … #define ADPA_HSYNC_CNTL_ENABLE … #define ADPA_VSYNC_ACTIVE_HIGH … #define ADPA_VSYNC_ACTIVE_LOW … #define ADPA_HSYNC_ACTIVE_HIGH … #define ADPA_HSYNC_ACTIVE_LOW … #define FPA0 … #define FPA1 … #define FPB0 … #define FPB1 … #define FP_N_DIV_MASK … #define FP_N_DIV_SHIFT … #define FP_M1_DIV_MASK … #define FP_M1_DIV_SHIFT … #define FP_M2_DIV_MASK … #define FP_M2_DIV_SHIFT … #define PORT_HOTPLUG_EN … #define HDMIB_HOTPLUG_INT_EN … #define HDMIC_HOTPLUG_INT_EN … #define HDMID_HOTPLUG_INT_EN … #define SDVOB_HOTPLUG_INT_EN … #define SDVOC_HOTPLUG_INT_EN … #define TV_HOTPLUG_INT_EN … #define CRT_HOTPLUG_INT_EN … #define CRT_HOTPLUG_FORCE_DETECT … /* CDV.. */ #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 … #define CRT_HOTPLUG_DAC_ON_TIME_2M … #define CRT_HOTPLUG_DAC_ON_TIME_4M … #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 … #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 … #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 … #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 … #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK … #define CRT_HOTPLUG_DETECT_DELAY_1G … #define CRT_HOTPLUG_DETECT_DELAY_2G … #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV … #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV … #define CRT_HOTPLUG_DETECT_MASK … #define PORT_HOTPLUG_STAT … #define CRT_HOTPLUG_INT_STATUS … #define TV_HOTPLUG_INT_STATUS … #define CRT_HOTPLUG_MONITOR_MASK … #define CRT_HOTPLUG_MONITOR_COLOR … #define CRT_HOTPLUG_MONITOR_MONO … #define CRT_HOTPLUG_MONITOR_NONE … #define SDVOC_HOTPLUG_INT_STATUS … #define SDVOB_HOTPLUG_INT_STATUS … #define SDVOB … #define SDVOC … #define SDVO_ENABLE … #define SDVO_PIPE_B_SELECT … #define SDVO_STALL_SELECT … #define SDVO_INTERRUPT_ENABLE … #define SDVO_COLOR_RANGE_16_235 … #define SDVO_AUDIO_ENABLE … /** * 915G/GM SDVO pixel multiplier. * * Programmed value is multiplier - 1, up to 5x. * * DPLL_MD_UDI_MULTIPLIER_MASK */ #define SDVO_PORT_MULTIPLY_MASK … #define SDVO_PORT_MULTIPLY_SHIFT … #define SDVO_PHASE_SELECT_MASK … #define SDVO_PHASE_SELECT_DEFAULT … #define SDVO_CLOCK_OUTPUT_INVERT … #define SDVOC_GANG_MODE … #define SDVO_BORDER_ENABLE … #define SDVOB_PCIE_CONCURRENCY … #define SDVO_DETECTED … /* Bits to be preserved when writing */ #define SDVOB_PRESERVE_MASK … #define SDVOC_PRESERVE_MASK … /* * This register controls the LVDS output enable, pipe selection, and data * format selection. * * All of the clock/data pairs are force powered down by power sequencing. */ #define LVDS … /* * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ #define LVDS_PORT_EN … /* Selects pipe B for LVDS data. Must be set on pre-965. */ #define LVDS_PIPEB_SELECT … /* Turns on border drawing to allow centered display. */ #define LVDS_BORDER_EN … /* * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per * pixel. */ #define LVDS_A0A2_CLKA_POWER_MASK … #define LVDS_A0A2_CLKA_POWER_DOWN … #define LVDS_A0A2_CLKA_POWER_UP … /* * Controls the A3 data pair, which contains the additional LSBs for 24 bit * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be * on. */ #define LVDS_A3_POWER_MASK … #define LVDS_A3_POWER_DOWN … #define LVDS_A3_POWER_UP … /* * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP * is set. */ #define LVDS_CLKB_POWER_MASK … #define LVDS_CLKB_POWER_DOWN … #define LVDS_CLKB_POWER_UP … /* * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 * setting for whether we are in dual-channel mode. The B3 pair will * additionally only be powered up when LVDS_A3_POWER_UP is set. */ #define LVDS_B0B3_POWER_MASK … #define LVDS_B0B3_POWER_DOWN … #define LVDS_B0B3_POWER_UP … #define PIPEACONF … #define PIPEACONF_ENABLE … #define PIPEACONF_DISABLE … #define PIPEACONF_DOUBLE_WIDE … #define PIPECONF_ACTIVE … #define PIPECONF_DSIPLL_LOCK … #define PIPEACONF_SINGLE_WIDE … #define PIPEACONF_PIPE_UNLOCKED … #define PIPEACONF_DSR … #define PIPEACONF_PIPE_LOCKED … #define PIPEACONF_PALETTE … #define PIPECONF_FORCE_BORDER … #define PIPEACONF_GAMMA … #define PIPECONF_PROGRESSIVE … #define PIPECONF_INTERLACE_W_FIELD_INDICATION … #define PIPECONF_INTERLACE_FIELD_0_ONLY … #define PIPECONF_PLANE_OFF … #define PIPECONF_CURSOR_OFF … #define PIPEBCONF … #define PIPEBCONF_ENABLE … #define PIPEBCONF_DISABLE … #define PIPEBCONF_DOUBLE_WIDE … #define PIPEBCONF_DISABLE … #define PIPEBCONF_GAMMA … #define PIPEBCONF_PALETTE … #define PIPECCONF … #define PIPEBGCMAXRED … #define PIPEBGCMAXGREEN … #define PIPEBGCMAXBLUE … #define PIPEASTAT … #define PIPEBSTAT … #define PIPECSTAT … #define PIPE_VBLANK_INTERRUPT_STATUS … #define PIPE_START_VBLANK_INTERRUPT_STATUS … #define PIPE_VBLANK_CLEAR … #define PIPE_VBLANK_STATUS … #define PIPE_TE_STATUS … #define PIPE_DPST_EVENT_STATUS … #define PIPE_VSYNC_CLEAR … #define PIPE_VSYNC_STATUS … #define PIPE_HDMI_AUDIO_UNDERRUN_STATUS … #define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS … #define PIPE_VBLANK_INTERRUPT_ENABLE … #define PIPE_START_VBLANK_INTERRUPT_ENABLE … #define PIPE_TE_ENABLE … #define PIPE_LEGACY_BLC_EVENT_ENABLE … #define PIPE_DPST_EVENT_ENABLE … #define PIPE_VSYNC_ENABL … #define PIPE_HDMI_AUDIO_UNDERRUN … #define PIPE_HDMI_AUDIO_BUFFER_DONE … #define PIPE_FIFO_UNDERRUN … #define PIPE_HDMI_AUDIO_INT_MASK … #define PIPE_EVENT_MASK … #define PIPE_VBLANK_MASK … #define HISTOGRAM_INT_CONTROL … #define HISTOGRAM_BIN_DATA … #define HISTOGRAM_LOGIC_CONTROL … #define PWM_CONTROL_LOGIC … #define PIPE_HOTPLUG_INTERRUPT_STATUS … #define HISTOGRAM_INTERRUPT_ENABLE … #define HISTOGRAM_LOGIC_ENABLE … #define PWM_LOGIC_ENABLE … #define PWM_PHASEIN_ENABLE … #define PWM_PHASEIN_INT_ENABLE … #define PWM_PHASEIN_VB_COUNT … #define PWM_PHASEIN_INC … #define HISTOGRAM_INT_CTRL_CLEAR … #define DPST_YUV_LUMA_MODE … #define PIPEAFRAMEHIGH … #define PIPEAFRAMEPIXEL … #define PIPEBFRAMEHIGH … #define PIPEBFRAMEPIXEL … #define PIPECFRAMEHIGH … #define PIPECFRAMEPIXEL … #define PIPE_FRAME_HIGH_MASK … #define PIPE_FRAME_HIGH_SHIFT … #define PIPE_FRAME_LOW_MASK … #define PIPE_FRAME_LOW_SHIFT … #define PIPE_PIXEL_MASK … #define PIPE_PIXEL_SHIFT … #define FW_BLC_SELF … #define FW_BLC_SELF_EN … #define DSPARB … #define DSPFW1 … #define DSP_FIFO_SR_WM_MASK … #define DSP_FIFO_SR_WM_SHIFT … #define CURSOR_B_FIFO_WM_MASK … #define CURSOR_B_FIFO_WM_SHIFT … #define DSPFW2 … #define CURSOR_A_FIFO_WM_MASK … #define CURSOR_A_FIFO_WM_SHIFT … #define DSP_PLANE_C_FIFO_WM_MASK … #define DSP_PLANE_C_FIFO_WM_SHIFT … #define DSPFW3 … #define DSPFW4 … #define DSPFW5 … #define DSP_PLANE_B_FIFO_WM1_SHIFT … #define DSP_PLANE_A_FIFO_WM1_SHIFT … #define CURSOR_B_FIFO_WM1_SHIFT … #define CURSOR_FIFO_SR_WM1_SHIFT … #define DSPFW6 … #define DSPCHICKENBIT … #define DSPACNTR … #define DSPBCNTR … #define DSPCCNTR … #define DISPLAY_PLANE_ENABLE … #define DISPLAY_PLANE_DISABLE … #define DISPPLANE_GAMMA_ENABLE … #define DISPPLANE_GAMMA_DISABLE … #define DISPPLANE_PIXFORMAT_MASK … #define DISPPLANE_8BPP … #define DISPPLANE_15_16BPP … #define DISPPLANE_16BPP … #define DISPPLANE_32BPP_NO_ALPHA … #define DISPPLANE_32BPP … #define DISPPLANE_STEREO_ENABLE … #define DISPPLANE_STEREO_DISABLE … #define DISPPLANE_SEL_PIPE_MASK … #define DISPPLANE_SEL_PIPE_POS … #define DISPPLANE_SEL_PIPE_A … #define DISPPLANE_SEL_PIPE_B … #define DISPPLANE_SRC_KEY_ENABLE … #define DISPPLANE_SRC_KEY_DISABLE … #define DISPPLANE_LINE_DOUBLE … #define DISPPLANE_NO_LINE_DOUBLE … #define DISPPLANE_STEREO_POLARITY_FIRST … #define DISPPLANE_STEREO_POLARITY_SECOND … /* plane B only */ #define DISPPLANE_ALPHA_TRANS_ENABLE … #define DISPPLANE_ALPHA_TRANS_DISABLE … #define DISPPLANE_SPRITE_ABOVE_DISPLAYA … #define DISPPLANE_SPRITE_ABOVE_OVERLAY … #define DISPPLANE_BOTTOM … #define DSPABASE … #define DSPALINOFF … #define DSPASTRIDE … #define DSPBBASE … #define DSPBLINOFF … #define DSPBADDR … #define DSPBSTRIDE … #define DSPCBASE … #define DSPCLINOFF … #define DSPCSTRIDE … #define DSPAKEYVAL … #define DSPAKEYMASK … #define DSPAPOS … #define DSPASIZE … #define DSPBPOS … #define DSPBSIZE … #define DSPCPOS … #define DSPCSIZE … #define DSPASURF … #define DSPATILEOFF … #define DSPBSURF … #define DSPBTILEOFF … #define DSPCSURF … #define DSPCTILEOFF … #define DSPCKEYMAXVAL … #define DSPCKEYMINVAL … #define DSPCKEYMSK … #define VGACNTRL … #define VGA_DISP_DISABLE … #define VGA_2X_MODE … #define VGA_PIPE_B_SELECT … /* * Overlay registers */ #define OV_C_OFFSET … #define OV_OVADD … #define OV_DOVASTA … #define OV_PIPE_SELECT … #define OV_PIPE_SELECT_POS … #define OV_PIPE_A … #define OV_PIPE_C … #define OV_OGAMC5 … #define OV_OGAMC4 … #define OV_OGAMC3 … #define OV_OGAMC2 … #define OV_OGAMC1 … #define OV_OGAMC0 … #define OVC_OVADD … #define OVC_DOVCSTA … #define OVC_OGAMC5 … #define OVC_OGAMC4 … #define OVC_OGAMC3 … #define OVC_OGAMC2 … #define OVC_OGAMC1 … #define OVC_OGAMC0 … /* * Some BIOS scratch area registers. The 845 (and 830?) store the amount * of video memory available to the BIOS in SWF1. */ #define SWF0 … #define SWF1 … #define SWF2 … #define SWF3 … #define SWF4 … #define SWF5 … #define SWF6 … /* * 855 scratch registers. */ #define SWF00 … #define SWF01 … #define SWF02 … #define SWF03 … #define SWF04 … #define SWF05 … #define SWF06 … #define SWF10 … #define SWF11 … #define SWF12 … #define SWF13 … #define SWF14 … #define SWF15 … #define SWF16 … #define SWF30 … #define SWF31 … #define SWF32 … /* * Palette registers */ #define PALETTE_A … #define PALETTE_B … #define PALETTE_C … /* Cursor A & B regs */ #define CURACNTR … #define CURSOR_MODE_DISABLE … #define CURSOR_MODE_64_32B_AX … #define CURSOR_MODE_64_ARGB_AX … #define MCURSOR_GAMMA_ENABLE … #define CURABASE … #define CURAPOS … #define CURSOR_POS_MASK … #define CURSOR_POS_SIGN … #define CURSOR_X_SHIFT … #define CURSOR_Y_SHIFT … #define CURBCNTR … #define CURBBASE … #define CURBPOS … #define CURCCNTR … #define CURCBASE … #define CURCPOS … /* * Interrupt Registers */ #define IER … #define IIR … #define IMR … #define ISR … /* * MOORESTOWN delta registers */ #define MRST_DPLL_A … #define DPLLA_MODE_LVDS … #define MRST_FPA0 … #define MRST_FPA1 … #define MRST_PERF_MODE … /* * MEDFIELD HDMI registers */ #define HDMIPHYMISCCTL … #define HDMI_PHY_POWER_DOWN … #define HDMIB_CONTROL … #define HDMIB_PORT_EN … #define HDMIB_PIPE_B_SELECT … #define HDMIB_NULL_PACKET … #define HDMIB_HDCP_PORT … /* #define LVDS 0x61180 */ #define MRST_PANEL_8TO6_DITHER_ENABLE … #define MRST_PANEL_24_DOT_1_FORMAT … #define LVDS_A3_POWER_UP_0_OUTPUT … #define MIPI … #define MIPI_C … #define MIPI_PORT_EN … /* Turns on border drawing to allow centered display. */ #define SEL_FLOPPED_HSTX … #define PASS_FROM_SPHY_TO_AFE … #define MIPI_BORDER_EN … #define MIPIA_3LANE_MIPIC_1LANE … #define MIPIA_2LANE_MIPIC_2LANE … #define TE_TRIGGER_DSI_PROTOCOL … #define TE_TRIGGER_GPIO_PIN … #define MIPI_TE_COUNT … /* #define PP_CONTROL 0x61204 */ #define POWER_DOWN_ON_RESET … /* #define PFIT_CONTROL 0x61230 */ #define PFIT_PIPE_SELECT … #define PFIT_PIPE_SELECT_SHIFT … /* #define BLC_PWM_CTL 0x61254 */ #define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT … #define MRST_BACKLIGHT_MODULATION_FREQ_MASK … /* #define PIPEACONF 0x70008 */ #define PIPEACONF_PIPE_STATE … /* #define DSPACNTR 0x70180 */ #define MRST_DSPABASE … #define MRST_DSPBBASE … /* * Moorestown registers. */ /* * MIPI IP registers */ #define MIPIC_REG_OFFSET … #define DEVICE_READY_REG … #define LP_OUTPUT_HOLD … #define EXIT_ULPS_DEV_READY … #define LP_OUTPUT_HOLD_RELEASE … #define ENTERING_ULPS … #define EXITING_ULPS … #define ULPS_MASK … #define BUS_POSSESSION … #define INTR_STAT_REG … #define RX_SOT_ERROR … #define RX_SOT_SYNC_ERROR … #define RX_ESCAPE_MODE_ENTRY_ERROR … #define RX_LP_TX_SYNC_ERROR … #define RX_HS_RECEIVE_TIMEOUT_ERROR … #define RX_FALSE_CONTROL_ERROR … #define RX_ECC_SINGLE_BIT_ERROR … #define RX_ECC_MULTI_BIT_ERROR … #define RX_CHECKSUM_ERROR … #define RX_DSI_DATA_TYPE_NOT_RECOGNIZED … #define RX_DSI_VC_ID_INVALID … #define TX_FALSE_CONTROL_ERROR … #define TX_ECC_SINGLE_BIT_ERROR … #define TX_ECC_MULTI_BIT_ERROR … #define TX_CHECKSUM_ERROR … #define TX_DSI_DATA_TYPE_NOT_RECOGNIZED … #define TX_DSI_VC_ID_INVALID … #define HIGH_CONTENTION … #define LOW_CONTENTION … #define DPI_FIFO_UNDER_RUN … #define HS_TX_TIMEOUT … #define LP_RX_TIMEOUT … #define TURN_AROUND_ACK_TIMEOUT … #define ACK_WITH_NO_ERROR … #define HS_GENERIC_WR_FIFO_FULL … #define LP_GENERIC_WR_FIFO_FULL … #define SPL_PKT_SENT … #define INTR_EN_REG … #define DSI_FUNC_PRG_REG … #define DPI_CHANNEL_NUMBER_POS … #define DBI_CHANNEL_NUMBER_POS … #define FMT_DPI_POS … #define FMT_DBI_POS … #define DBI_DATA_WIDTH_POS … /* DPI PIXEL FORMATS */ #define RGB_565_FMT … #define RGB_666_FMT … #define LRGB_666_FMT … #define RGB_888_FMT … #define VIRTUAL_CHANNEL_NUMBER_0 … #define VIRTUAL_CHANNEL_NUMBER_1 … #define VIRTUAL_CHANNEL_NUMBER_2 … #define VIRTUAL_CHANNEL_NUMBER_3 … #define DBI_NOT_SUPPORTED … #define DBI_DATA_WIDTH_16BIT … #define DBI_DATA_WIDTH_9BIT … #define DBI_DATA_WIDTH_8BIT … #define DBI_DATA_WIDTH_OPT1 … #define DBI_DATA_WIDTH_OPT2 … #define HS_TX_TIMEOUT_REG … #define LP_RX_TIMEOUT_REG … #define TURN_AROUND_TIMEOUT_REG … #define DEVICE_RESET_REG … #define DPI_RESOLUTION_REG … #define RES_V_POS … #define HORIZ_SYNC_PAD_COUNT_REG … #define HORIZ_BACK_PORCH_COUNT_REG … #define HORIZ_FRONT_PORCH_COUNT_REG … #define HORIZ_ACTIVE_AREA_COUNT_REG … #define VERT_SYNC_PAD_COUNT_REG … #define VERT_BACK_PORCH_COUNT_REG … #define VERT_FRONT_PORCH_COUNT_REG … #define HIGH_LOW_SWITCH_COUNT_REG … #define DPI_CONTROL_REG … #define DPI_SHUT_DOWN … #define DPI_TURN_ON … #define DPI_COLOR_MODE_ON … #define DPI_COLOR_MODE_OFF … #define DPI_BACK_LIGHT_ON … #define DPI_BACK_LIGHT_OFF … #define DPI_LP … #define DPI_DATA_REG … #define DPI_BACK_LIGHT_ON_DATA … #define DPI_BACK_LIGHT_OFF_DATA … #define INIT_COUNT_REG … #define MAX_RET_PAK_REG … #define VIDEO_FMT_REG … #define COMPLETE_LAST_PCKT … #define EOT_DISABLE_REG … #define ENABLE_CLOCK_STOPPING … #define LP_BYTECLK_REG … #define LP_GEN_DATA_REG … #define HS_GEN_DATA_REG … #define LP_GEN_CTRL_REG … #define HS_GEN_CTRL_REG … #define DCS_CHANNEL_NUMBER_POS … #define MCS_COMMANDS_POS … #define WORD_COUNTS_POS … #define MCS_PARAMETER_POS … #define GEN_FIFO_STAT_REG … #define HS_DATA_FIFO_FULL … #define HS_DATA_FIFO_HALF_EMPTY … #define HS_DATA_FIFO_EMPTY … #define LP_DATA_FIFO_FULL … #define LP_DATA_FIFO_HALF_EMPTY … #define LP_DATA_FIFO_EMPTY … #define HS_CTRL_FIFO_FULL … #define HS_CTRL_FIFO_HALF_EMPTY … #define HS_CTRL_FIFO_EMPTY … #define LP_CTRL_FIFO_FULL … #define LP_CTRL_FIFO_HALF_EMPTY … #define LP_CTRL_FIFO_EMPTY … #define DBI_FIFO_EMPTY … #define DPI_FIFO_EMPTY … #define HS_LS_DBI_ENABLE_REG … #define TXCLKESC_REG … #define DPHY_PARAM_REG … #define DBI_BW_CTRL_REG … #define CLK_LANE_SWT_REG … /* * MIPI Adapter registers */ #define MIPI_CONTROL_REG … #define MIPI_2X_CLOCK_BITS … #define MIPI_DATA_ADDRESS_REG … #define MIPI_DATA_LENGTH_REG … #define MIPI_COMMAND_ADDRESS_REG … #define MIPI_COMMAND_LENGTH_REG … #define MIPI_READ_DATA_RETURN_REG0 … #define MIPI_READ_DATA_RETURN_REG1 … #define MIPI_READ_DATA_RETURN_REG2 … #define MIPI_READ_DATA_RETURN_REG3 … #define MIPI_READ_DATA_RETURN_REG4 … #define MIPI_READ_DATA_RETURN_REG5 … #define MIPI_READ_DATA_RETURN_REG6 … #define MIPI_READ_DATA_RETURN_REG7 … #define MIPI_READ_DATA_VALID_REG … /* DBI COMMANDS */ #define soft_reset … /* * The display module performs a software reset. * Registers are written with their SW Reset default values. */ #define get_power_mode … /* * The display module returns the current power mode */ #define get_address_mode … /* * The display module returns the current status. */ #define get_pixel_format … /* * This command gets the pixel format for the RGB image data * used by the interface. */ #define get_display_mode … /* * The display module returns the Display Image Mode status. */ #define get_signal_mode … /* * The display module returns the Display Signal Mode. */ #define get_diagnostic_result … /* * The display module returns the self-diagnostic results following * a Sleep Out command. */ #define enter_sleep_mode … /* * This command causes the display module to enter the Sleep mode. * In this mode, all unnecessary blocks inside the display module are * disabled except interface communication. This is the lowest power * mode the display module supports. */ #define exit_sleep_mode … /* * This command causes the display module to exit Sleep mode. * All blocks inside the display module are enabled. */ #define enter_partial_mode … /* * This command causes the display module to enter the Partial Display * Mode. The Partial Display Mode window is described by the * set_partial_area command. */ #define enter_normal_mode … /* * This command causes the display module to enter the Normal mode. * Normal Mode is defined as Partial Display mode and Scroll mode are off */ #define exit_invert_mode … /* * This command causes the display module to stop inverting the image * data on the display device. The frame memory contents remain unchanged. * No status bits are changed. */ #define enter_invert_mode … /* * This command causes the display module to invert the image data only on * the display device. The frame memory contents remain unchanged. * No status bits are changed. */ #define set_gamma_curve … /* * This command selects the desired gamma curve for the display device. * Four fixed gamma curves are defined in section DCS spec. */ #define set_display_off … /* ************************************************************************* *\ This command causes the display module to stop displaying the image data on the display device. The frame memory contents remain unchanged. No status bits are changed. \* ************************************************************************* */ #define set_display_on … /* ************************************************************************* *\ This command causes the display module to start displaying the image data on the display device. The frame memory contents remain unchanged. No status bits are changed. \* ************************************************************************* */ #define set_column_address … /* * This command defines the column extent of the frame memory accessed by * the hostprocessor with the read_memory_continue and * write_memory_continue commands. * No status bits are changed. */ #define set_page_addr … /* * This command defines the page extent of the frame memory accessed by * the host processor with the write_memory_continue and * read_memory_continue command. * No status bits are changed. */ #define write_mem_start … /* * This command transfers image data from the host processor to the * display modules frame memory starting at the pixel location specified * by preceding set_column_address and set_page_address commands. */ #define set_partial_area … /* * This command defines the Partial Display mode s display area. * There are two parameters associated with this command, the first * defines the Start Row (SR) and the second the End Row (ER). SR and ER * refer to the Frame Memory Line Pointer. */ #define set_scroll_area … /* * This command defines the display modules Vertical Scrolling Area. */ #define set_tear_off … /* * This command turns off the display modules Tearing Effect output * signal on the TE signal line. */ #define set_tear_on … /* * This command turns on the display modules Tearing Effect output signal * on the TE signal line. */ #define set_address_mode … /* * This command sets the data order for transfers from the host processor * to display modules frame memory,bits B[7:5] and B3, and from the * display modules frame memory to the display device, bits B[2:0] and B4. */ #define set_scroll_start … /* * This command sets the start of the vertical scrolling area in the frame * memory. The vertical scrolling area is fully defined when this command * is used with the set_scroll_area command The set_scroll_start command * has one parameter, the Vertical Scroll Pointer. The VSP defines the * line in the frame memory that is written to the display device as the * first line of the vertical scroll area. */ #define exit_idle_mode … /* * This command causes the display module to exit Idle mode. */ #define enter_idle_mode … /* * This command causes the display module to enter Idle Mode. * In Idle Mode, color expression is reduced. Colors are shown on the * display device using the MSB of each of the R, G and B color * components in the frame memory */ #define set_pixel_format … /* * This command sets the pixel format for the RGB image data used by the * interface. * Bits D[6:4] DPI Pixel Format Definition * Bits D[2:0] DBI Pixel Format Definition * Bits D7 and D3 are not used. */ #define DCS_PIXEL_FORMAT_3bpp … #define DCS_PIXEL_FORMAT_8bpp … #define DCS_PIXEL_FORMAT_12bpp … #define DCS_PIXEL_FORMAT_16bpp … #define DCS_PIXEL_FORMAT_18bpp … #define DCS_PIXEL_FORMAT_24bpp … #define write_mem_cont … /* * This command transfers image data from the host processor to the * display module's frame memory continuing from the pixel location * following the previous write_memory_continue or write_memory_start * command. */ #define set_tear_scanline … /* * This command turns on the display modules Tearing Effect output signal * on the TE signal line when the display module reaches line N. */ #define get_scanline … /* * The display module returns the current scanline, N, used to update the * display device. The total number of scanlines on a display device is * defined as VSYNC + VBP + VACT + VFP.The first scanline is defined as * the first line of V Sync and is denoted as Line 0. * When in Sleep Mode, the value returned by get_scanline is undefined. */ /* MCS or Generic COMMANDS */ /* MCS/generic data type */ #define GEN_SHORT_WRITE_0 … #define GEN_SHORT_WRITE_1 … #define GEN_SHORT_WRITE_2 … #define GEN_READ_0 … #define GEN_READ_1 … #define GEN_READ_2 … #define GEN_LONG_WRITE … #define MCS_SHORT_WRITE_0 … #define MCS_SHORT_WRITE_1 … #define MCS_READ … #define MCS_LONG_WRITE … /* MCS/generic commands */ /* TPO MCS */ #define write_display_profile … #define write_display_brightness … #define write_ctrl_display … #define write_ctrl_cabc … #define UI_IMAGE … #define STILL_IMAGE … #define MOVING_IMAGE … #define write_hysteresis … #define write_gamma_setting … #define write_cabc_min_bright … #define write_kbbc_profile … /* TMD MCS */ #define tmd_write_display_brightness … /* * This command is used to control ambient light, panel backlight * brightness and gamma settings. */ #define BRIGHT_CNTL_BLOCK_ON … #define AMBIENT_LIGHT_SENSE_ON … #define DISPLAY_DIMMING_ON … #define BACKLIGHT_ON … #define DISPLAY_BRIGHTNESS_AUTO … #define GAMMA_AUTO … /* DCS Interface Pixel Formats */ #define DCS_PIXEL_FORMAT_3BPP … #define DCS_PIXEL_FORMAT_8BPP … #define DCS_PIXEL_FORMAT_12BPP … #define DCS_PIXEL_FORMAT_16BPP … #define DCS_PIXEL_FORMAT_18BPP … #define DCS_PIXEL_FORMAT_24BPP … /* ONE PARAMETER READ DATA */ #define addr_mode_data … #define diag_res_data … #define disp_mode_data … #define pxl_fmt_data … #define pwr_mode_data … #define sig_mode_data … /* TWO PARAMETERS READ DATA */ #define scanline_data1 … #define scanline_data2 … #define NON_BURST_MODE_SYNC_PULSE … #define NON_BURST_MODE_SYNC_EVENTS … #define BURST_MODE … #define DBI_COMMAND_BUFFER_SIZE … /* Allocate at least * 0x100 Byte with 32 * byte alignment */ #define DBI_DATA_BUFFER_SIZE … #define DBI_CB_TIME_OUT … #define GEN_FB_TIME_OUT … #define SKU_83 … #define SKU_100 … #define SKU_100L … #define SKU_BYPASS … /* Some handy macros for playing with bitfields. */ #define PSB_MASK(high, low) … #define SET_FIELD(value, field) … #define GET_FIELD(word, field) … #define _PIPE(pipe, a, b) … /* PCI config space */ #define SB_PCKT … #define SB_OPCODE_MASK … #define SB_OPCODE_SHIFT … #define SB_OPCODE_READ … #define SB_OPCODE_WRITE … #define SB_DEST_MASK … #define SB_DEST_SHIFT … #define SB_DEST_DPLL … #define SB_BYTE_ENABLE_MASK … #define SB_BYTE_ENABLE_SHIFT … #define SB_BUSY … #define DSPCLK_GATE_D … #define VRHUNIT_CLOCK_GATE_DISABLE … #define DPOUNIT_CLOCK_GATE_DISABLE … #define DPIOUNIT_CLOCK_GATE_DISABLE … #define DPUNIT_PIPEB_GATE_DISABLE … #define DPUNIT_PIPEA_GATE_DISABLE … #define DPCUNIT_CLOCK_GATE_DISABLE … #define DPLSUNIT_CLOCK_GATE_DISABLE … #define RAMCLK_GATE_D … /* 32-bit value read/written from the DPIO reg. */ #define SB_DATA … /* 32-bit address of the DPIO reg to be read/written. */ #define SB_ADDR … #define DPIO_CFG … #define DPIO_MODE_SELECT_1 … #define DPIO_MODE_SELECT_0 … #define DPIO_SFR_BYPASS … /* reset is active low */ #define DPIO_CMN_RESET_N … /* Cedarview sideband registers */ #define _SB_M_A … #define _SB_M_B … #define SB_M(pipe) … #define SB_M_DIVIDER_MASK … #define SB_M_DIVIDER_SHIFT … #define _SB_N_VCO_A … #define _SB_N_VCO_B … #define SB_N_VCO(pipe) … #define SB_N_VCO_SEL_MASK … #define SB_N_VCO_SEL_SHIFT … #define SB_N_DIVIDER_MASK … #define SB_N_DIVIDER_SHIFT … #define SB_N_CB_TUNE_MASK … #define SB_N_CB_TUNE_SHIFT … /* the bit 14:13 is used to select between the different reference clock for Pipe A/B */ #define SB_REF_DPLLA … #define SB_REF_DPLLB … #define REF_CLK_MASK … #define REF_CLK_CORE … #define REF_CLK_DPLL … #define REF_CLK_DPLLA … /* For the DPLL B, it will use the reference clk from DPLL A when using (2 << 13) */ #define _SB_REF_A … #define _SB_REF_B … #define SB_REF_SFR(pipe) … #define _SB_P_A … #define _SB_P_B … #define SB_P(pipe) … #define SB_P2_DIVIDER_MASK … #define SB_P2_DIVIDER_SHIFT … #define SB_P2_10 … #define SB_P2_5 … #define SB_P2_14 … #define SB_P2_7 … #define SB_P1_DIVIDER_MASK … #define SB_P1_DIVIDER_SHIFT … #define PSB_LANE0 … #define PSB_LANE1 … #define PSB_LANE2 … #define PSB_LANE3 … #define LANE_PLL_MASK … #define LANE_PLL_ENABLE … #define LANE_PLL_PIPE(p) … #define DP_B … #define DP_C … #define DP_PORT_EN … #define DP_PIPEB_SELECT … #define DP_PIPE_MASK … /* Link training mode - select a suitable mode for each stage */ #define DP_LINK_TRAIN_PAT_1 … #define DP_LINK_TRAIN_PAT_2 … #define DP_LINK_TRAIN_PAT_IDLE … #define DP_LINK_TRAIN_OFF … #define DP_LINK_TRAIN_MASK … #define DP_LINK_TRAIN_SHIFT … /* Signal voltages. These are mostly controlled by the other end */ #define DP_VOLTAGE_0_4 … #define DP_VOLTAGE_0_6 … #define DP_VOLTAGE_0_8 … #define DP_VOLTAGE_1_2 … #define DP_VOLTAGE_MASK … #define DP_VOLTAGE_SHIFT … /* Signal pre-emphasis levels, like voltages, the other end tells us what * they want */ #define DP_PRE_EMPHASIS_0 … #define DP_PRE_EMPHASIS_3_5 … #define DP_PRE_EMPHASIS_6 … #define DP_PRE_EMPHASIS_9_5 … #define DP_PRE_EMPHASIS_MASK … #define DP_PRE_EMPHASIS_SHIFT … /* How many wires to use. I guess 3 was too hard */ #define DP_PORT_WIDTH_1 … #define DP_PORT_WIDTH_2 … #define DP_PORT_WIDTH_4 … #define DP_PORT_WIDTH_MASK … /* Mystic DPCD version 1.1 special mode */ #define DP_ENHANCED_FRAMING … /** locked once port is enabled */ #define DP_PORT_REVERSAL … /** sends the clock on lane 15 of the PEG for debug */ #define DP_CLOCK_OUTPUT_ENABLE … #define DP_SCRAMBLING_DISABLE … #define DP_SCRAMBLING_DISABLE_IRONLAKE … /** limit RGB values to avoid confusing TVs */ #define DP_COLOR_RANGE_16_235 … /** Turn on the audio link */ #define DP_AUDIO_OUTPUT_ENABLE … /** vs and hs sync polarity */ #define DP_SYNC_VS_HIGH … #define DP_SYNC_HS_HIGH … /** A fantasy */ #define DP_DETECTED … /** The aux channel provides a way to talk to the * signal sink for DDC etc. Max packet size supported * is 20 bytes in each direction, hence the 5 fixed * data registers */ #define DPB_AUX_CH_CTL … #define DPB_AUX_CH_DATA1 … #define DPB_AUX_CH_DATA2 … #define DPB_AUX_CH_DATA3 … #define DPB_AUX_CH_DATA4 … #define DPB_AUX_CH_DATA5 … #define DPC_AUX_CH_CTL … #define DPC_AUX_CH_DATA1 … #define DPC_AUX_CH_DATA2 … #define DPC_AUX_CH_DATA3 … #define DPC_AUX_CH_DATA4 … #define DPC_AUX_CH_DATA5 … #define DP_AUX_CH_CTL_SEND_BUSY … #define DP_AUX_CH_CTL_DONE … #define DP_AUX_CH_CTL_INTERRUPT … #define DP_AUX_CH_CTL_TIME_OUT_ERROR … #define DP_AUX_CH_CTL_TIME_OUT_400us … #define DP_AUX_CH_CTL_TIME_OUT_600us … #define DP_AUX_CH_CTL_TIME_OUT_800us … #define DP_AUX_CH_CTL_TIME_OUT_1600us … #define DP_AUX_CH_CTL_TIME_OUT_MASK … #define DP_AUX_CH_CTL_RECEIVE_ERROR … #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK … #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT … #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK … #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT … #define DP_AUX_CH_CTL_AUX_AKSV_SELECT … #define DP_AUX_CH_CTL_MANCHESTER_TEST … #define DP_AUX_CH_CTL_SYNC_TEST … #define DP_AUX_CH_CTL_DEGLITCH_TEST … #define DP_AUX_CH_CTL_PRECHARGE_TEST … #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK … #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT … /* * Computing GMCH M and N values for the Display Port link * * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes * * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) * * The GMCH value is used internally * * bytes_per_pixel is the number of bytes coming out of the plane, * which is after the LUTs, so we want the bytes for our color format. * For our current usage, this is always 3, one byte for R, G and B. */ #define _PIPEA_GMCH_DATA_M … #define _PIPEB_GMCH_DATA_M … /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ #define PIPE_GMCH_DATA_M_TU_SIZE_MASK … #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT … #define PIPE_GMCH_DATA_M_MASK … #define _PIPEA_GMCH_DATA_N … #define _PIPEB_GMCH_DATA_N … #define PIPE_GMCH_DATA_N_MASK … /* * Computing Link M and N values for the Display Port link * * Link M / N = pixel_clock / ls_clk * * (the DP spec calls pixel_clock the 'strm_clk') * * The Link value is transmitted in the Main Stream * Attributes and VB-ID. */ #define _PIPEA_DP_LINK_M … #define _PIPEB_DP_LINK_M … #define PIPEA_DP_LINK_M_MASK … #define _PIPEA_DP_LINK_N … #define _PIPEB_DP_LINK_N … #define PIPEA_DP_LINK_N_MASK … #define PIPE_GMCH_DATA_M(pipe) … #define PIPE_GMCH_DATA_N(pipe) … #define PIPE_DP_LINK_M(pipe) … #define PIPE_DP_LINK_N(pipe) … #define PIPE_BPC_MASK … #define PIPE_8BPC … #define PIPE_10BPC … #define PIPE_6BPC … #endif
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