/* SPDX-License-Identifier: MIT */ #ifndef __AST_REG_H__ #define __AST_REG_H__ #include <linux/bits.h> /* * Modesetting */ #define AST_IO_MM_OFFSET … #define AST_IO_MM_LENGTH … #define AST_IO_VGAARI_W … #define AST_IO_VGAMR_W … #define AST_IO_VGAMR_R … #define AST_IO_VGAMR_IOSEL … #define AST_IO_VGAER … #define AST_IO_VGAER_VGA_ENABLE … #define AST_IO_VGASRI … #define AST_IO_VGASR1_SD … #define AST_IO_VGADRR … #define AST_IO_VGADWR … #define AST_IO_VGAPDR … #define AST_IO_VGAGRI … #define AST_IO_VGACRI … #define AST_IO_VGACR80_PASSWORD … #define AST_IO_VGACRA1_VGAIO_DISABLED … #define AST_IO_VGACRA1_MMIO_ENABLED … #define AST_IO_VGACRB6_HSYNC_OFF … #define AST_IO_VGACRB6_VSYNC_OFF … #define AST_IO_VGACRCB_HWC_16BPP … #define AST_IO_VGACRCB_HWC_ENABLED … #define AST_IO_VGAIR1_R … #define AST_IO_VGAIR1_VREFRESH … /* * Display Transmitter Type */ #define TX_TYPE_MASK … #define NO_TX … #define ITE66121_VBIOS_TX … #define SI164_VBIOS_TX … #define CH7003_VBIOS_TX … #define DP501_VBIOS_TX … #define ANX9807_VBIOS_TX … #define TX_FW_EMBEDDED_FW_TX … #define ASTDP_DPMCU_TX … #define AST_VRAM_INIT_STATUS_MASK … //#define AST_VRAM_INIT_BY_BMC BIT(7) //#define AST_VRAM_INIT_READY BIT(6) /* * AST DisplayPort */ /* Define for Soc scratched reg used on ASTDP */ #define AST_DP_PHY_SLEEP … #define AST_DP_VIDEO_ENABLE … /* * CRD1[b5]: DP MCU FW is executing * CRDC[b0]: DP link success * CRDF[b0]: DP HPD * CRE5[b0]: Host reading EDID process is done */ #define ASTDP_MCU_FW_EXECUTING … #define ASTDP_LINK_SUCCESS … #define ASTDP_HPD … #define ASTDP_HOST_EDID_READ_DONE … #define ASTDP_HOST_EDID_READ_DONE_MASK … /* * CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE * Precondition: A. ~AST_DP_PHY_SLEEP && * B. DP_HPD && * C. DP_LINK_SUCCESS */ #define ASTDP_MIRROR_VIDEO_ENABLE … #define ASTDP_EDID_READ_POINTER_MASK … #define ASTDP_EDID_VALID_FLAG_MASK … #define ASTDP_EDID_READ_DATA_MASK … /* * ASTDP setmode registers: * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp) * CRE1[7:0]: MISC1 (default: 0x00) * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50) */ #define ASTDP_MISC0_24bpp … #define ASTDP_MISC1 … #define ASTDP_AND_CLEAR_MASK … #endif
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