/* * Copyright 2012 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * */ /* * Authors: Dave Airlie <[email protected]> */ #include <linux/delay.h> #include <linux/pci.h> #include <drm/drm_print.h> #include "ast_dram_tables.h" #include "ast_drv.h" static void ast_post_chip_2300(struct drm_device *dev); static void ast_post_chip_2500(struct drm_device *dev); static const u8 extreginfo[] = …; static const u8 extreginfo_ast2300[] = …; static void ast_set_def_ext_reg(struct drm_device *dev) { … } static u32 __ast_mindwm(void __iomem *regs, u32 r) { … } static void __ast_moutdwm(void __iomem *regs, u32 r, u32 v) { … } u32 ast_mindwm(struct ast_device *ast, u32 r) { … } void ast_moutdwm(struct ast_device *ast, u32 r, u32 v) { … } /* * AST2100/2150 DLL CBR Setting */ #define CBR_SIZE_AST2150 … #define CBR_PASSNUM_AST2150 … #define CBR_THRESHOLD_AST2150 … #define CBR_THRESHOLD2_AST2150 … #define TIMEOUT_AST2150 … #define CBR_PATNUM_AST2150 … static const u32 pattern_AST2150[14] = …; static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen) { … } #if 0 /* unused in DDX driver - here for completeness */ static u32 mmctestsingle2_ast2150(struct ast_device *ast, u32 datagen) { u32 data, timeout; ast_moutdwm(ast, 0x1e6e0070, 0x00000000); ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3)); timeout = 0; do { data = ast_mindwm(ast, 0x1e6e0070) & 0x40; if (++timeout > TIMEOUT_AST2150) { ast_moutdwm(ast, 0x1e6e0070, 0x00000000); return 0xffffffff; } } while (!data); data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7; ast_moutdwm(ast, 0x1e6e0070, 0x00000000); return data; } #endif static int cbrtest_ast2150(struct ast_device *ast) { … } static int cbrscan_ast2150(struct ast_device *ast, int busw) { … } static void cbrdlli_ast2150(struct ast_device *ast, int busw) { … } static void ast_init_dram_reg(struct drm_device *dev) { … } void ast_post_gpu(struct drm_device *dev) { … } /* AST 2300 DRAM settings */ #define AST_DDR3 … #define AST_DDR2 … struct ast2300_dram_param { … }; /* * DQSI DLL CBR Setting */ #define CBR_SIZE0 … #define CBR_SIZE1 … #define CBR_SIZE2 … #define CBR_PASSNUM … #define CBR_PASSNUM2 … #define CBR_THRESHOLD … #define CBR_THRESHOLD2 … #define TIMEOUT … #define CBR_PATNUM … static const u32 pattern[8] = …; static bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl) { … } static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl) { … } static bool mmc_test_burst(struct ast_device *ast, u32 datagen) { … } static u32 mmc_test_burst2(struct ast_device *ast, u32 datagen) { … } static bool mmc_test_single(struct ast_device *ast, u32 datagen) { … } static u32 mmc_test_single2(struct ast_device *ast, u32 datagen) { … } static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen) { … } static int cbr_test(struct ast_device *ast) { … } static int cbr_scan(struct ast_device *ast) { … } static u32 cbr_test2(struct ast_device *ast) { … } static u32 cbr_scan2(struct ast_device *ast) { … } static bool cbr_test3(struct ast_device *ast) { … } static bool cbr_scan3(struct ast_device *ast) { … } static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param) { … } /* finetuneDQI_L */ static void finetuneDQSI(struct ast_device *ast) { … } static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param) { … } /* CBRDLL2 */ static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param) { … } static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param) { … } static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param) { … } static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param) { … } static void ast_post_chip_2300(struct drm_device *dev) { … } static bool cbr_test_2500(struct ast_device *ast) { … } static bool ddr_test_2500(struct ast_device *ast) { … } static void ddr_init_common_2500(struct ast_device *ast) { … } static void ddr_phy_init_2500(struct ast_device *ast) { … } /* * Check DRAM Size * 1Gb : 0x80000000 ~ 0x87FFFFFF * 2Gb : 0x80000000 ~ 0x8FFFFFFF * 4Gb : 0x80000000 ~ 0x9FFFFFFF * 8Gb : 0x80000000 ~ 0xBFFFFFFF */ static void check_dram_size_2500(struct ast_device *ast, u32 tRFC) { … } static void enable_cache_2500(struct ast_device *ast) { … } static void set_mpll_2500(struct ast_device *ast) { … } static void reset_mmc_2500(struct ast_device *ast) { … } static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table) { … } static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table) { … } static bool ast_dram_init_2500(struct ast_device *ast) { … } void ast_patch_ahb_2500(void __iomem *regs) { … } void ast_post_chip_2500(struct drm_device *dev) { … }
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