/* SPDX-License-Identifier: GPL-2.0 */ /* * RZ/G2L MIPI DSI Interface Registers Definitions * * Copyright (C) 2022 Renesas Electronics Corporation */ #ifndef __RZG2L_MIPI_DSI_REGS_H__ #define __RZG2L_MIPI_DSI_REGS_H__ #include <linux/bits.h> /* DPHY Registers */ #define DSIDPHYCTRL0 … #define DSIDPHYCTRL0_CAL_EN_HSRX_OFS … #define DSIDPHYCTRL0_CMN_MASTER_EN … #define DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 … #define DSIDPHYCTRL0_EN_LDO1200 … #define DSIDPHYCTRL0_EN_BGR … #define DSIDPHYTIM0 … #define DSIDPHYTIM0_TCLK_MISS(x) … #define DSIDPHYTIM0_T_INIT(x) … #define DSIDPHYTIM1 … #define DSIDPHYTIM1_THS_PREPARE(x) … #define DSIDPHYTIM1_TCLK_PREPARE(x) … #define DSIDPHYTIM1_THS_SETTLE(x) … #define DSIDPHYTIM1_TCLK_SETTLE(x) … #define DSIDPHYTIM2 … #define DSIDPHYTIM2_TCLK_TRAIL(x) … #define DSIDPHYTIM2_TCLK_POST(x) … #define DSIDPHYTIM2_TCLK_PRE(x) … #define DSIDPHYTIM2_TCLK_ZERO(x) … #define DSIDPHYTIM3 … #define DSIDPHYTIM3_TLPX(x) … #define DSIDPHYTIM3_THS_EXIT(x) … #define DSIDPHYTIM3_THS_TRAIL(x) … #define DSIDPHYTIM3_THS_ZERO(x) … /* --------------------------------------------------------*/ /* Link Registers */ #define LINK_REG_OFFSET … /* Link Status Register */ #define LINKSR … #define LINKSR_LPBUSY … #define LINKSR_HSBUSY … #define LINKSR_VICHRUN1 … #define LINKSR_SQCHRUN1 … #define LINKSR_SQCHRUN0 … /* Tx Set Register */ #define TXSETR … #define TXSETR_NUMLANECAP … #define TXSETR_DLEN … #define TXSETR_CLEN … #define TXSETR_NUMLANEUSE(x) … /* HS Clock Set Register */ #define HSCLKSETR … #define HSCLKSETR_HSCLKMODE_CONT … #define HSCLKSETR_HSCLKMODE_NON_CONT … #define HSCLKSETR_HSCLKRUN_HS … #define HSCLKSETR_HSCLKRUN_LP … /* Reset Control Register */ #define RSTCR … #define RSTCR_SWRST … #define RSTCR_FCETXSTP … /* Reset Status Register */ #define RSTSR … #define RSTSR_DL0DIR … #define RSTSR_DLSTPST … #define RSTSR_SWRSTV1 … #define RSTSR_SWRSTIB … #define RSTSR_SWRSTAPB … #define RSTSR_SWRSTLP … #define RSTSR_SWRSTHS … /* Clock Lane Stop Time Set Register */ #define CLSTPTSETR … #define CLSTPTSETR_CLKKPT(x) … #define CLSTPTSETR_CLKBFHT(x) … #define CLSTPTSETR_CLKSTPT(x) … /* LP Transition Time Set Register */ #define LPTRNSTSETR … #define LPTRNSTSETR_GOLPBKT(x) … /* Physical Lane Status Register */ #define PLSR … #define PLSR_CLHS2LP … #define PLSR_CLLP2HS … /* Video-Input Channel 1 Set 0 Register */ #define VICH1SET0R … #define VICH1SET0R_VSEN … #define VICH1SET0R_HFPNOLP … #define VICH1SET0R_HBPNOLP … #define VICH1SET0R_HSANOLP … #define VICH1SET0R_VSTPAFT … #define VICH1SET0R_VSTART … /* Video-Input Channel 1 Set 1 Register */ #define VICH1SET1R … #define VICH1SET1R_DLY(x) … /* Video-Input Channel 1 Status Register */ #define VICH1SR … #define VICH1SR_VIRDY … #define VICH1SR_RUNNING … #define VICH1SR_STOP … #define VICH1SR_START … /* Video-Input Channel 1 Pixel Packet Set Register */ #define VICH1PPSETR … #define VICH1PPSETR_DT_RGB18 … #define VICH1PPSETR_DT_RGB18_LS … #define VICH1PPSETR_DT_RGB24 … #define VICH1PPSETR_TXESYNC_PULSE … #define VICH1PPSETR_VC(x) … /* Video-Input Channel 1 Vertical Size Set Register */ #define VICH1VSSETR … #define VICH1VSSETR_VACTIVE(x) … #define VICH1VSSETR_VSPOL_LOW … #define VICH1VSSETR_VSPOL_HIGH … #define VICH1VSSETR_VSA(x) … /* Video-Input Channel 1 Vertical Porch Set Register */ #define VICH1VPSETR … #define VICH1VPSETR_VFP(x) … #define VICH1VPSETR_VBP(x) … /* Video-Input Channel 1 Horizontal Size Set Register */ #define VICH1HSSETR … #define VICH1HSSETR_HACTIVE(x) … #define VICH1HSSETR_HSPOL_LOW … #define VICH1HSSETR_HSPOL_HIGH … #define VICH1HSSETR_HSA(x) … /* Video-Input Channel 1 Horizontal Porch Set Register */ #define VICH1HPSETR … #define VICH1HPSETR_HFP(x) … #define VICH1HPSETR_HBP(x) … #endif /* __RZG2L_MIPI_DSI_REGS_H__ */
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