/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2013 Red Hat * Author: Rob Clark <[email protected]> */ #ifndef __MSM_GPU_H__ #define __MSM_GPU_H__ #include <linux/adreno-smmu-priv.h> #include <linux/clk.h> #include <linux/devfreq.h> #include <linux/interconnect.h> #include <linux/pm_opp.h> #include <linux/regulator/consumer.h> #include "msm_drv.h" #include "msm_fence.h" #include "msm_ringbuffer.h" #include "msm_gem.h" struct msm_gem_submit; struct msm_gpu_perfcntr; struct msm_gpu_state; struct msm_file_private; struct msm_gpu_config { … }; /* So far, with hardware that I've seen to date, we can have: * + zero, one, or two z180 2d cores * + a3xx or a2xx 3d core, which share a common CP (the firmware * for the CP seems to implement some different PM4 packet types * but the basics of cmdstream submission are the same) * * Which means that the eventual complete "class" hierarchy, once * support for all past and present hw is in place, becomes: * + msm_gpu * + adreno_gpu * + a3xx_gpu * + a2xx_gpu * + z180_gpu */ struct msm_gpu_funcs { … }; /* Additional state for iommu faults: */ struct msm_gpu_fault_info { … }; /** * struct msm_gpu_devfreq - devfreq related state */ struct msm_gpu_devfreq { … }; struct msm_gpu { … }; static inline struct msm_gpu *dev_to_gpu(struct device *dev) { … } /* It turns out that all targets use the same ringbuffer size */ #define MSM_GPU_RINGBUFFER_SZ … #define MSM_GPU_RINGBUFFER_BLKSIZE … #define MSM_GPU_RB_CNTL_DEFAULT … static inline bool msm_gpu_active(struct msm_gpu *gpu) { … } /* Perf-Counters: * The select_reg and select_val are just there for the benefit of the child * class that actually enables the perf counter.. but msm_gpu base class * will handle sampling/displaying the counters. */ struct msm_gpu_perfcntr { … }; /* * The number of priority levels provided by drm gpu scheduler. The * DRM_SCHED_PRIORITY_KERNEL priority level is treated specially in some * cases, so we don't use it (no need for kernel generated jobs). */ #define NR_SCHED_PRIORITIES … /** * struct msm_file_private - per-drm_file context * * @queuelock: synchronizes access to submitqueues list * @submitqueues: list of &msm_gpu_submitqueue created by userspace * @queueid: counter incremented each time a submitqueue is created, * used to assign &msm_gpu_submitqueue.id * @aspace: the per-process GPU address-space * @ref: reference count * @seqno: unique per process seqno */ struct msm_file_private { … }; /** * msm_gpu_convert_priority - Map userspace priority to ring # and sched priority * * @gpu: the gpu instance * @prio: the userspace priority level * @ring_nr: [out] the ringbuffer the userspace priority maps to * @sched_prio: [out] the gpu scheduler priority level which the userspace * priority maps to * * With drm/scheduler providing it's own level of prioritization, our total * number of available priority levels is (nr_rings * NR_SCHED_PRIORITIES). * Each ring is associated with it's own scheduler instance. However, our * UABI is that lower numerical values are higher priority. So mapping the * single userspace priority level into ring_nr and sched_prio takes some * care. The userspace provided priority (when a submitqueue is created) * is mapped to ring nr and scheduler priority as such: * * ring_nr = userspace_prio / NR_SCHED_PRIORITIES * sched_prio = NR_SCHED_PRIORITIES - * (userspace_prio % NR_SCHED_PRIORITIES) - 1 * * This allows generations without preemption (nr_rings==1) to have some * amount of prioritization, and provides more priority levels for gens * that do have preemption. */ static inline int msm_gpu_convert_priority(struct msm_gpu *gpu, int prio, unsigned *ring_nr, enum drm_sched_priority *sched_prio) { … } /** * struct msm_gpu_submitqueues - Userspace created context. * * A submitqueue is associated with a gl context or vk queue (or equiv) * in userspace. * * @id: userspace id for the submitqueue, unique within the drm_file * @flags: userspace flags for the submitqueue, specified at creation * (currently unusued) * @ring_nr: the ringbuffer used by this submitqueue, which is determined * by the submitqueue's priority * @faults: the number of GPU hangs associated with this submitqueue * @last_fence: the sequence number of the last allocated fence (for error * checking) * @ctx: the per-drm_file context associated with the submitqueue (ie. * which set of pgtables do submits jobs associated with the * submitqueue use) * @node: node in the context's list of submitqueues * @fence_idr: maps fence-id to dma_fence for userspace visible fence * seqno, protected by submitqueue lock * @idr_lock: for serializing access to fence_idr * @lock: submitqueue lock for serializing submits on a queue * @ref: reference count * @entity: the submit job-queue */ struct msm_gpu_submitqueue { … }; struct msm_gpu_state_bo { … }; struct msm_gpu_state { … }; static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) { … } static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) { … } static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) { … } static inline u64 gpu_read64(struct msm_gpu *gpu, u32 reg) { … } static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val) { … } int msm_gpu_pm_suspend(struct msm_gpu *gpu); int msm_gpu_pm_resume(struct msm_gpu *gpu); void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx, struct drm_printer *p); int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx); struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx, u32 id); int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, u32 prio, u32 flags, u32 *id); int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx, struct drm_msm_submitqueue_query *args); int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id); void msm_submitqueue_close(struct msm_file_private *ctx); void msm_submitqueue_destroy(struct kref *kref); int msm_file_private_set_sysprof(struct msm_file_private *ctx, struct msm_gpu *gpu, int sysprof); void __msm_file_private_destroy(struct kref *kref); static inline void msm_file_private_put(struct msm_file_private *ctx) { … } static inline struct msm_file_private *msm_file_private_get( struct msm_file_private *ctx) { … } void msm_devfreq_init(struct msm_gpu *gpu); void msm_devfreq_cleanup(struct msm_gpu *gpu); void msm_devfreq_resume(struct msm_gpu *gpu); void msm_devfreq_suspend(struct msm_gpu *gpu); void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor); void msm_devfreq_active(struct msm_gpu *gpu); void msm_devfreq_idle(struct msm_gpu *gpu); int msm_gpu_hw_init(struct msm_gpu *gpu); void msm_gpu_perfcntr_start(struct msm_gpu *gpu); void msm_gpu_perfcntr_stop(struct msm_gpu *gpu); int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs); void msm_gpu_retire(struct msm_gpu *gpu); void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit); int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, const char *name, struct msm_gpu_config *config); struct msm_gem_address_space * msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task); void msm_gpu_cleanup(struct msm_gpu *gpu); struct msm_gpu *adreno_load_gpu(struct drm_device *dev); void __init adreno_register(void); void __exit adreno_unregister(void); static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue) { … } static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu) { … } static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu) { … } /* * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can * support expanded privileges */ #define check_apriv(gpu, flags) … #endif /* __MSM_GPU_H__ */
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