/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2013 Red Hat * Author: Rob Clark <[email protected]> * * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved. */ #ifndef __ADRENO_GPU_H__ #define __ADRENO_GPU_H__ #include <linux/firmware.h> #include <linux/iopoll.h> #include "msm_gpu.h" #include "adreno_common.xml.h" #include "adreno_pm4.xml.h" extern bool snapshot_debugbus; extern bool allow_vram_carveout; enum { … }; /** * @enum adreno_family: identify generation and possibly sub-generation * * In some cases there are distinct sub-generations within a major revision * so it helps to be able to group the GPU devices by generation and if * necessary sub-generation. */ enum adreno_family { … }; #define ADRENO_QUIRK_TWO_PASS_USE_WFI … #define ADRENO_QUIRK_FAULT_DETECT_MASK … #define ADRENO_QUIRK_LMLOADKILL_DISABLE … #define ADRENO_QUIRK_HAS_HW_APRIV … #define ADRENO_QUIRK_HAS_CACHED_COHERENT … /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. */ #define ADRENO_CHIPID_FMT … #define ADRENO_CHIPID_ARGS(_c) … struct adreno_gpu_funcs { … }; struct adreno_reglist { … }; struct adreno_speedbin { … }; struct a6xx_info; struct adreno_info { … }; #define ADRENO_CHIP_IDS(tbl...) … struct adreno_gpulist { … }; #define DECLARE_ADRENO_GPULIST(name) … /* * Helper to build a speedbin table, ie. the table: * fuse | speedbin * -----+--------- * 0 | 0 * 169 | 1 * 174 | 2 * * would be declared as: * * .speedbins = ADRENO_SPEEDBINS( * { 0, 0 }, * { 169, 1 }, * { 174, 2 }, * ), */ #define ADRENO_SPEEDBINS(tbl...) … struct adreno_protect { … }; #define DECLARE_ADRENO_PROTECT(name, __count_max) … struct adreno_gpu { … }; #define to_adreno_gpu(x) … struct adreno_ocmem { … }; /* platform config data (ie. from DT, or pdata) */ struct adreno_platform_config { … }; #define ADRENO_IDLE_TIMEOUT … #define spin_until(X) … static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu) { … } static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn) { … } static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) { … } static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) { … } static inline bool adreno_is_a20x(const struct adreno_gpu *gpu) { … } static inline bool adreno_is_a225(const struct adreno_gpu *gpu) { … } static inline bool adreno_is_a305(const struct adreno_gpu *gpu) { … } static inline bool adreno_is_a305b(const struct adreno_gpu *gpu) { … } static inline bool adreno_is_a306(const struct adreno_gpu *gpu) { … } static inline bool adreno_is_a320(const struct adreno_gpu *gpu) { … } static inline bool adreno_is_a330(const struct adreno_gpu *gpu) { … } static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a405(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a420(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a430(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a505(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a506(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a508(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a509(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a510(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a512(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a530(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a540(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a610(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a618(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a619(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a619_holi(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a630(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a640(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a650(const struct adreno_gpu *gpu) { … } static inline int adreno_is_7c3(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a660(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a680(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a690(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a702(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a610_family(const struct adreno_gpu *gpu) { … } /* check for a615, a616, a618, a619 or any a630 derivatives */ static inline int adreno_is_a630_family(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a660_family(const struct adreno_gpu *gpu) { … } /* check for a650, a660, or any derivatives */ static inline int adreno_is_a650_family(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a640_family(const struct adreno_gpu *gpu) { … } static inline int adreno_is_a730(struct adreno_gpu *gpu) { … } static inline int adreno_is_a740(struct adreno_gpu *gpu) { … } static inline int adreno_is_a750(struct adreno_gpu *gpu) { … } static inline int adreno_is_x185(struct adreno_gpu *gpu) { … } static inline int adreno_is_a740_family(struct adreno_gpu *gpu) { … } static inline int adreno_is_a7xx(struct adreno_gpu *gpu) { … } u64 adreno_private_address_space_size(struct msm_gpu *gpu); int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, uint32_t param, uint64_t *value, uint32_t *len); int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx, uint32_t param, uint64_t value, uint32_t len); const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname); struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, const struct firmware *fw, u64 *iova); int adreno_hw_init(struct msm_gpu *gpu); void adreno_recover(struct msm_gpu *gpu); void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg); bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, struct drm_printer *p); #endif void adreno_dump_info(struct msm_gpu *gpu); void adreno_dump(struct msm_gpu *gpu); void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords); struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu); int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, struct adreno_ocmem *ocmem); void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem); int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs, int nr_rings); void adreno_gpu_cleanup(struct adreno_gpu *gpu); int adreno_load_fw(struct adreno_gpu *adreno_gpu); void adreno_gpu_state_destroy(struct msm_gpu_state *state); int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state); int adreno_gpu_state_put(struct msm_gpu_state *state); void adreno_show_object(struct drm_printer *p, void **ptr, int len, bool *encoded); /* * Common helper function to initialize the default address space for arm-smmu * attached targets */ struct msm_gem_address_space * adreno_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev); struct msm_gem_address_space * adreno_iommu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev, unsigned long quirks); int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); int adreno_read_speedbin(struct device *dev, u32 *speedbin); /* * For a5xx and a6xx targets load the zap shader that is used to pull the GPU * out of secure mode */ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid); /* ringbuffer helpers (the parts that are adreno specific) */ static inline void OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) { … } /* no-op packet: */ static inline void OUT_PKT2(struct msm_ringbuffer *ring) { … } static inline void OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) { … } static inline u32 PM4_PARITY(u32 val) { … } /* Maximum number of values that can be executed for one opcode */ #define TYPE4_MAX_PAYLOAD … #define PKT4(_reg, _cnt) … static inline void OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) { … } static inline void OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) { … } struct msm_gpu *a2xx_gpu_init(struct drm_device *dev); struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); struct msm_gpu *a5xx_gpu_init(struct drm_device *dev); struct msm_gpu *a6xx_gpu_init(struct drm_device *dev); static inline uint32_t get_wptr(struct msm_ringbuffer *ring) { … } /* * Given a register and a count, return a value to program into * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len * registers starting at _reg. * * The register base needs to be a multiple of the length. If it is not, the * hardware will quietly mask off the bits for you and shift the size. For * example, if you intend the protection to start at 0x07 for a length of 4 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might * expose registers you intended to protect! */ #define ADRENO_PROTECT_RW(_reg, _len) … /* * Same as above, but allow reads over the range. For areas of mixed use (such * as performance counters) this allows us to protect a much larger range with a * single register */ #define ADRENO_PROTECT_RDONLY(_reg, _len) … #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) … #endif /* __ADRENO_GPU_H__ */
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