linux/drivers/gpu/drm/msm/adreno/a6xx_gmu.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2017 The Linux Foundation. All rights reserved. */

#ifndef _A6XX_GMU_H_
#define _A6XX_GMU_H_

#include <linux/completion.h>
#include <linux/iopoll.h>
#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <linux/soc/qcom/qcom_aoss.h>
#include "msm_drv.h"
#include "a6xx_hfi.h"

struct a6xx_gmu_bo { … };

/*
 * These define the different GMU wake up options - these define how both the
 * CPU and the GMU bring up the hardware
 */

/* THe GMU has already been booted and the rentention registers are active */
#define GMU_WARM_BOOT …

/* the GMU is coming up for the first time or back from a power collapse */
#define GMU_COLD_BOOT …

/*
 * These define the level of control that the GMU has - the higher the number
 * the more things that the GMU hardware controls on its own.
 */

/* The GMU does not do any idle state management */
#define GMU_IDLE_STATE_ACTIVE …

/* The GMU manages SPTP power collapse */
#define GMU_IDLE_STATE_SPTP …

/* The GMU does automatic IFPC (intra-frame power collapse) */
#define GMU_IDLE_STATE_IFPC …

struct a6xx_gmu { … };

static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
{ … }

static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
{ … }

static inline void
gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)
{ … }

static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
{ … }

static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
{ … }

#define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) …

static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
{ … }

static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
{ … }

#define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) …

/*
 * These are the available OOB (out of band requests) to the GMU where "out of
 * band" means that the CPU talks to the GMU directly and not through HFI.
 * Normally this works by writing a ITCM/DTCM register and then triggering a
 * interrupt (the "request" bit) and waiting for an acknowledgment (the "ack"
 * bit). The state is cleared by writing the "clear' bit to the GMU interrupt.
 *
 * These are used to force the GMU/GPU to stay on during a critical sequence or
 * for hardware workarounds.
 */

enum a6xx_gmu_oob_state { … };

void a6xx_hfi_init(struct a6xx_gmu *gmu);
int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
void a6xx_hfi_stop(struct a6xx_gmu *gmu);
int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu);
int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index);

bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
void a6xx_sptprac_disable(struct a6xx_gmu *gmu);
int a6xx_sptprac_enable(struct a6xx_gmu *gmu);

#endif