linux/drivers/gpu/drm/msm/adreno/a5xx_power.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2016 The Linux Foundation. All rights reserved.
 */

#include <linux/pm_opp.h>
#include "a5xx_gpu.h"

/*
 * The GPMU data block is a block of shared registers that can be used to
 * communicate back and forth. These "registers" are by convention with the GPMU
 * firwmare and not bound to any specific hardware design
 */

#define AGC_INIT_BASE …
#define AGC_INIT_MSG_MAGIC …
#define AGC_MSG_BASE …

#define AGC_MSG_STATE …
#define AGC_MSG_COMMAND …
#define AGC_MSG_PAYLOAD_SIZE …
#define AGC_MSG_PAYLOAD(_o) …

#define AGC_POWER_CONFIG_PRODUCTION_ID …
#define AGC_INIT_MSG_VALUE …

/* AGC_LM_CONFIG (A540+) */
#define AGC_LM_CONFIG …
#define AGC_LM_CONFIG_GPU_VERSION_SHIFT …
#define AGC_LM_CONFIG_ENABLE_GPMU_ADAPTIVE …
#define AGC_LM_CONFIG_THROTTLE_DISABLE …
#define AGC_LM_CONFIG_ISENSE_ENABLE …
#define AGC_LM_CONFIG_ENABLE_ERROR …
#define AGC_LM_CONFIG_LLM_ENABLED …
#define AGC_LM_CONFIG_BCL_DISABLED …

#define AGC_LEVEL_CONFIG …

static struct { … } a5xx_sequence_regs[] = …;

/*
 * Get the actual voltage value for the operating point at the specified
 * frequency
 */
static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq)
{ … }

/* Setup thermal limit management */
static void a530_lm_setup(struct msm_gpu *gpu)
{ … }

#define PAYLOAD_SIZE(_size) …
#define LM_DCVS_LIMIT …
#define LEVEL_CONFIG …

static void a540_lm_setup(struct msm_gpu *gpu)
{ … }

/* Enable SP/TP cpower collapse */
static void a5xx_pc_init(struct msm_gpu *gpu)
{ … }

/* Enable the GPMU microcontroller */
static int a5xx_gpmu_init(struct msm_gpu *gpu)
{ … }

/* Enable limits management */
static void a5xx_lm_enable(struct msm_gpu *gpu)
{ … }

int a5xx_power_init(struct msm_gpu *gpu)
{ … }

void a5xx_gpmu_ucode_init(struct msm_gpu *gpu)
{ … }