linux/drivers/gpu/drm/msm/adreno/a5xx_gpu.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/cpumask.h>
#include <linux/firmware/qcom/qcom_scm.h>
#include <linux/pm_opp.h>
#include <linux/nvmem-consumer.h>
#include <linux/slab.h>
#include "msm_gem.h"
#include "msm_mmu.h"
#include "a5xx_gpu.h"

extern bool hang_debug;
static void a5xx_dump(struct msm_gpu *gpu);

#define GPU_PAS_ID …

static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
{ … }

void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
		bool sync)
{ … }

static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit)
{ … }

static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
{ … }

static const struct adreno_five_hwcg_regs { … } a5xx_hwcg[] = …, a50x_hwcg[] = …, a512_hwcg[] = …;

void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
{ … }

static int a5xx_me_init(struct msm_gpu *gpu)
{ … }

static int a5xx_preempt_start(struct msm_gpu *gpu)
{ … }

static void a5xx_ucode_check_version(struct a5xx_gpu *a5xx_gpu,
		struct drm_gem_object *obj)
{ … }

static int a5xx_ucode_load(struct msm_gpu *gpu)
{ … }

#define SCM_GPU_ZAP_SHADER_RESUME …

static int a5xx_zap_shader_resume(struct msm_gpu *gpu)
{ … }

static int a5xx_zap_shader_init(struct msm_gpu *gpu)
{ … }

#define A5XX_INT_MASK …

static int a5xx_hw_init(struct msm_gpu *gpu)
{ … }

static void a5xx_recover(struct msm_gpu *gpu)
{ … }

static void a5xx_destroy(struct msm_gpu *gpu)
{ … }

static inline bool _a5xx_check_idle(struct msm_gpu *gpu)
{ … }

bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
{ … }

static int a5xx_fault_handler(void *arg, unsigned long iova, int flags, void *data)
{ … }

static void a5xx_cp_err_irq(struct msm_gpu *gpu)
{ … }

static void a5xx_rbbm_err_irq(struct msm_gpu *gpu, u32 status)
{ … }

static void a5xx_uche_err_irq(struct msm_gpu *gpu)
{ … }

static void a5xx_gpmu_err_irq(struct msm_gpu *gpu)
{ … }

static void a5xx_fault_detect_irq(struct msm_gpu *gpu)
{ … }

#define RBBM_ERROR_MASK …

static irqreturn_t a5xx_irq(struct msm_gpu *gpu)
{ … }

static const u32 a5xx_registers[] = …;

static void a5xx_dump(struct msm_gpu *gpu)
{ … }

static int a5xx_pm_resume(struct msm_gpu *gpu)
{ … }

static int a5xx_pm_suspend(struct msm_gpu *gpu)
{ … }

static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
{ … }

struct a5xx_crashdumper { … };

struct a5xx_gpu_state { … };

static int a5xx_crashdumper_init(struct msm_gpu *gpu,
		struct a5xx_crashdumper *dumper)
{ … }

static int a5xx_crashdumper_run(struct msm_gpu *gpu,
		struct a5xx_crashdumper *dumper)
{ … }

/*
 * These are a list of the registers that need to be read through the HLSQ
 * aperture through the crashdumper.  These are not nominally accessible from
 * the CPU on a secure platform.
 */
static const struct { … } a5xx_hlsq_aperture_regs[] = …;

static void a5xx_gpu_state_get_hlsq_regs(struct msm_gpu *gpu,
		struct a5xx_gpu_state *a5xx_state)
{ … }

static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu)
{ … }

static void a5xx_gpu_state_destroy(struct kref *kref)
{ … }

static int a5xx_gpu_state_put(struct msm_gpu_state *state)
{ … }


#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
static void a5xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
		      struct drm_printer *p)
{ … }
#endif

static struct msm_ringbuffer *a5xx_active_ring(struct msm_gpu *gpu)
{ … }

static u64 a5xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate)
{ … }

static uint32_t a5xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
{ … }

static const struct adreno_gpu_funcs funcs = …;

static void check_speed_bin(struct device *dev)
{ … }

struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
{ … }