linux/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
 */

#include <linux/clk-provider.h>
#include <linux/delay.h>

#include "hdmi.h"

#define HDMI_VCO_MAX_FREQ …
#define HDMI_VCO_MIN_FREQ …

#define HDMI_PCLK_MAX_FREQ …
#define HDMI_PCLK_MIN_FREQ …

#define HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD …
#define HDMI_DIG_FREQ_BIT_CLK_THRESHOLD …
#define HDMI_MID_FREQ_BIT_CLK_THRESHOLD …
#define HDMI_CORECLK_DIV …
#define HDMI_DEFAULT_REF_CLOCK …
#define HDMI_PLL_CMP_CNT …

#define HDMI_PLL_POLL_MAX_READS …
#define HDMI_PLL_POLL_TIMEOUT_US …

#define HDMI_NUM_TX_CHANNEL …

struct hdmi_pll_8996 { … };

#define hw_clk_to_pll(x) …

struct hdmi_8996_phy_pll_reg_cfg { … };

struct hdmi_8996_post_divider { … };

static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll)
{ … }

static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset,
				  u32 data)
{ … }

static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset)
{ … }

static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel,
				      int offset, int data)
{ … }

static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk,
				 bool gen_ssc)
{ … }

static inline u32 pll_get_rctrl(u64 frac_start, bool gen_ssc)
{ … }

static inline u32 pll_get_cctrl(u64 frac_start, bool gen_ssc)
{ … }

static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk,
					 bool gen_ssc)
{ … }

static inline u32 pll_get_pll_cmp(u64 fdata, unsigned long ref_clk)
{ … }

static inline u64 pll_cmp_to_fdata(u32 pll_cmp, unsigned long ref_clk)
{ … }

static int pll_get_post_div(struct hdmi_8996_post_divider *pd, u64 bclk)
{ … }

static int pll_calculate(unsigned long pix_clk, unsigned long ref_clk,
			 struct hdmi_8996_phy_pll_reg_cfg *cfg)
{ … }

static int hdmi_8996_pll_set_clk_rate(struct clk_hw *hw, unsigned long rate,
				      unsigned long parent_rate)
{ … }

static int hdmi_8996_phy_ready_status(struct hdmi_phy *phy)
{ … }

static int hdmi_8996_pll_lock_status(struct hdmi_pll_8996 *pll)
{ … }

static int hdmi_8996_pll_prepare(struct clk_hw *hw)
{ … }

static long hdmi_8996_pll_round_rate(struct clk_hw *hw,
				     unsigned long rate,
				     unsigned long *parent_rate)
{ … }

static unsigned long hdmi_8996_pll_recalc_rate(struct clk_hw *hw,
					       unsigned long parent_rate)
{ … }

static void hdmi_8996_pll_unprepare(struct clk_hw *hw)
{ … }

static int hdmi_8996_pll_is_enabled(struct clk_hw *hw)
{ … }

static const struct clk_ops hdmi_8996_pll_ops = …;

static const struct clk_init_data pll_init = …;

int msm_hdmi_pll_8996_init(struct platform_device *pdev)
{ … }

static const char * const hdmi_phy_8996_reg_names[] = …;

static const char * const hdmi_phy_8996_clk_names[] = …;

const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg = …;