linux/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <[email protected]>
 */

#include <linux/clk-provider.h>
#include <linux/delay.h>

#include "hdmi.h"

struct hdmi_pll_8960 { … };

#define hw_clk_to_pll(x) …

/*
 * HDMI PLL:
 *
 * To get the parent clock setup properly, we need to plug in hdmi pll
 * configuration into common-clock-framework.
 */

struct pll_rate { … };

/* NOTE: keep sorted highest freq to lowest: */
static const struct pll_rate freqtbl[] = …;

static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data)
{ … }

static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg)
{ … }

static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll)
{ … }

static int hdmi_pll_enable(struct clk_hw *hw)
{ … }

static void hdmi_pll_disable(struct clk_hw *hw)
{ … }

static const struct pll_rate *find_rate(unsigned long rate)
{ … }

static unsigned long hdmi_pll_recalc_rate(struct clk_hw *hw,
					  unsigned long parent_rate)
{ … }

static long hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long *parent_rate)
{ … }

static int hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
			     unsigned long parent_rate)
{ … }

static const struct clk_ops hdmi_pll_ops = …;

static const struct clk_parent_data hdmi_pll_parents[] = …;

static struct clk_init_data pll_init = …;

int msm_hdmi_pll_8960_init(struct platform_device *pdev)
{ … }