linux/drivers/gpu/drm/msm/adreno/a6xx_gpu.c

// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */


#include "msm_gem.h"
#include "msm_mmu.h"
#include "msm_gpu_trace.h"
#include "a6xx_gpu.h"
#include "a6xx_gmu.xml.h"

#include <linux/bitfield.h>
#include <linux/devfreq.h>
#include <linux/firmware/qcom/qcom_scm.h>
#include <linux/pm_domain.h>
#include <linux/soc/qcom/llcc-qcom.h>

#define GPU_PAS_ID …

static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
{ … }

static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
{ … }

static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
{ … }

static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
{ … }

static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
		u64 iova)
{ … }

static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
		struct msm_ringbuffer *ring, struct msm_file_private *ctx)
{ … }

static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
{ … }

static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
{ … }

static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
{ … }

static void a6xx_set_cp_protect(struct msm_gpu *gpu)
{ … }

static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
{ … }

static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
{ … }

static int a6xx_cp_init(struct msm_gpu *gpu)
{ … }

static int a7xx_cp_init(struct msm_gpu *gpu)
{ … }

/*
 * Check that the microcode version is new enough to include several key
 * security fixes. Return true if the ucode is safe.
 */
static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu,
		struct drm_gem_object *obj)
{ … }

static int a6xx_ucode_load(struct msm_gpu *gpu)
{ … }

static int a6xx_zap_shader_init(struct msm_gpu *gpu)
{ … }

#define A6XX_INT_MASK …

#define A7XX_INT_MASK …

#define A7XX_APRIV_MASK …

#define A7XX_BR_APRIVMASK …

static int hw_init(struct msm_gpu *gpu)
{ … }

static int a6xx_hw_init(struct msm_gpu *gpu)
{ … }

static void a6xx_dump(struct msm_gpu *gpu)
{ … }

static void a6xx_recover(struct msm_gpu *gpu)
{ … }

static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid)
{ … }

static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id)
{ … }

static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data)
{ … }

static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
{ … }

static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
{ … }

static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
{ … }

static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
{ … }

static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
{ … }

static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
{ … }

static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
{ … }

static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)
{ … }

static void a6xx_llc_slices_init(struct platform_device *pdev,
		struct a6xx_gpu *a6xx_gpu, bool is_a7xx)
{ … }

static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
{ … }


#define GBIF_CLIENT_HALT_MASK …
#define GBIF_ARB_HALT_MASK …
#define VBIF_XIN_HALT_CTRL0_MASK …
#define VBIF_RESET_ACK_MASK …
#define GPR0_GBIF_HALT_REQUEST …

void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off)
{ … }

void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert)
{ … }

static int a6xx_gmu_pm_resume(struct msm_gpu *gpu)
{ … }

static int a6xx_pm_resume(struct msm_gpu *gpu)
{ … }

static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu)
{ … }

static int a6xx_pm_suspend(struct msm_gpu *gpu)
{ … }

static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
{ … }

static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
{ … }

static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
{ … }

static void a6xx_destroy(struct msm_gpu *gpu)
{ … }

static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate)
{ … }

static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
			      bool suspended)
{ … }

static struct msm_gem_address_space *
a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
{ … }

static struct msm_gem_address_space *
a6xx_create_private_address_space(struct msm_gpu *gpu)
{ … }

static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
{ … }

static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
{ … }

static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse)
{ … }

static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info)
{ … }

static const struct adreno_gpu_funcs funcs = …;

static const struct adreno_gpu_funcs funcs_gmuwrapper = …;

static const struct adreno_gpu_funcs funcs_a7xx = …;

struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
{ … }