// SPDX-License-Identifier: GPL-2.0 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/interconnect.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/pm_opp.h> #include <soc/qcom/cmd-db.h> #include <drm/drm_gem.h> #include "a6xx_gpu.h" #include "a6xx_gmu.xml.h" #include "msm_gem.h" #include "msm_gpu_trace.h" #include "msm_mmu.h" static void a6xx_gmu_fault(struct a6xx_gmu *gmu) { … } static irqreturn_t a6xx_gmu_irq(int irq, void *data) { … } static irqreturn_t a6xx_hfi_irq(int irq, void *data) { … } bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) { … } /* Check to see if the GX rail is still powered */ bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) { … } void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, bool suspended) { … } unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) { … } static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) { … } /* Wait for the GMU to get to its most idle state */ int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) { … } static int a6xx_gmu_start(struct a6xx_gmu *gmu) { … } static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) { … } struct a6xx_gmu_oob_bits { … }; /* These are the interrupt / ack bits for each OOB request that are set * in a6xx_gmu_set_oob and a6xx_clear_oob */ static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = …; /* Trigger a OOB (out of band) request to the GMU */ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) { … } /* Clear a pending OOB state in the GMU */ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) { … } /* Enable CPU control of SPTP power power collapse */ int a6xx_sptprac_enable(struct a6xx_gmu *gmu) { … } /* Disable CPU control of SPTP power power collapse */ void a6xx_sptprac_disable(struct a6xx_gmu *gmu) { … } /* Let the GMU know we are starting a boot sequence */ static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) { … } /* Let the GMU know that we are about to go into slumber */ static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) { … } static int a6xx_rpmh_start(struct a6xx_gmu *gmu) { … } static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) { … } static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) { … } static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, const char *name); static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) { … } /* * The lowest 16 bits of this value are the number of XO clock cycles for main * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are * for the shorter hysteresis that happens after main - this is 0xa (.5 us) */ #define GMU_PWR_COL_HYST … /* Set up the idle state for the GMU */ static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) { … } struct block_header { … }; static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk) { … } static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) { … } static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) { … } #define A6XX_HFI_IRQ_MASK … #define A6XX_GMU_IRQ_MASK … static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) { … } static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) { … } /* Force the GMU off in case it isn't responsive */ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) { … } static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) { … } static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) { … } int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { … } bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) { … } /* Gracefully try to shut down the GMU and by extension the GPU */ static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) { … } int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) { … } static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu) { … } static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo, size_t size, u64 iova, const char *name) { … } static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) { … } /* Return the 'arc-level' for the given frequency */ static unsigned int a6xx_gmu_get_arc_level(struct device *dev, unsigned long freq) { … } static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, unsigned long *freqs, int freqs_count, const char *id) { … } /* * The GMU votes with the RPMh for itself and on behalf of the GPU but we need * to construct the list of votes on the CPU and send it over. Query the RPMh * voltage levels and build the votes */ static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) { … } static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, u32 size) { … } static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) { … } static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) { … } static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, const char *name) { … } static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, const char *name, irq_handler_t handler) { … } void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) { … } static int cxpd_notifier_cb(struct notifier_block *nb, unsigned long action, void *data) { … } int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) { … } int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) { … }
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